Re: [PATCH net-next v3] net: phy: dp83867: Add speed optimization feature
From: David Miller
Date: Fri Feb 21 2020 - 14:44:14 EST
From: Dan Murphy <dmurphy@xxxxxx>
Date: Tue, 18 Feb 2020 08:11:30 -0600
> Set the speed optimization bit on the DP83867 PHY.
> This feature can also be strapped on the 64 pin PHY devices
> but the 48 pin devices do not have the strap pin available to enable
> this feature in the hardware. PHY team suggests to have this bit set.
> With this bit set the PHY will auto negotiate and report the link
> parameters in the PHYSTS register. This register provides a single
> location within the register set for quick access to commonly accessed
> In this case when auto negotiation is on the PHY core reads the bits
> that have been configured or if auto negotiation is off the PHY core
> reads the BMCR register and sets the phydev parameters accordingly.
> This Giga bit PHY can throttle the speed to 100Mbps or 10Mbps to accomodate a
> 4-wire cable. If this should occur the PHYSTS register contains the
> current negotiated speed and duplex mode.
> In overriding the genphy_read_status the dp83867_read_status will do a
> genphy_read_status to setup the LP and pause bits. And then the PHYSTS
> register is read and the phydev speed and duplex mode settings are
> Signed-off-by: Dan Murphy <dmurphy@xxxxxx>
Applied to net-next, thank you.