Re: [PATCH] irq-gic-v3-its: fix access width for gicr_syncr

[Marc Zyngier]

On 2020-02-25 09:00, Heyi Guo wrote:
> GICR_SYNCR is a 32bit register, so it is better to access it with
> 32bit access width, though we have not seen any real problem.
>
> Signed-off-by: Heyi Guo <guoheyi@xxxxxxxxxx>
>
> ---
> Cc: Marc Zyngier <maz@xxxxxxxxxx>
> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> Cc: Jason Cooper <jason@xxxxxxxxxxxxxx>
> ---
>  drivers/irqchip/irq-gic-v3-its.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c 
> b/drivers/irqchip/irq-gic-v3-its.c
> index 65a11257d220..5c6790e3bfbf 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d,
> u8 clr, u8 set)
>
>  static void wait_for_syncr(void __iomem *rdbase)
>  {
> -	while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
> +	while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
>  		cpu_relax();
>  }

Yup, nice catch. Looks like no implementation really cares about it,
but still worth fixing.

I'll take it for 5.7.

Thanks,

        M.
--
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