Re: [RFC PATCH V3 00/11] riscv: Add vector ISA support

[LIU Zhiwei]

On 2020/3/9 11:41, Greentime Hu wrote:
> On Sun, Mar 8, 2020 at 5:50 PM <guoren@xxxxxxxxxx> wrote:
> > From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
> >
> > The implementation follow the RISC-V "V" Vector Extension draft v0.8 with
> > 128bit-vlen and it's based on linux-5.6-rc3 and tested with qemu [1].
> >
> > The patch implement basic context switch, sigcontext save/restore and
> > ptrace interface with a new regset NT_RISCV_VECTOR. Only fixed 128bit-vlen
> > is implemented. We need to discuss about vlen-size for libc sigcontext and
> > ptrace (the maximum size of vlen is unlimited in spec).
> >
> > Puzzle:
> > Dave Martin has talked "Growing CPU register state without breaking ABI" [2]
> > before, and riscv also met vlen size problem. Let's discuss the common issue
> > for all architectures and we need a better solution for unlimited vlen.
> >
> > Any help are welcomed :)
> >
> >   1: https://github.com/romanheros/qemu.git branch:vector-upstream-v3
> Hi Guo,
>
> Thanks for your patch.
> It seems the qemu repo doesn't have this branch?
Hi Greentime,

It's a promise from me. Now it's ready. You can turn on vector by 
"qemu-system-riscv64 -cpu rv64,v=true,vext_spec=v0.7.1".

Zhiwei