Re: [RFC PATCH 7/7] riscv: Explicit comment about user virtual address space size

From: Alex Ghiti
Date: Tue Apr 07 2020 - 01:15:10 EST




On 4/3/20 11:53 AM, Palmer Dabbelt wrote:
On Sun, 22 Mar 2020 04:00:28 PDT (-0700), alex@xxxxxxxx wrote:
Define precisely the size of the user accessible virtual space size
for sv32/39/48 mmu types and explain why the whole virtual address
space is split into 2 equal chunks between kernel and user space.

Signed-off-by: Alexandre Ghiti <alex@xxxxxxxx>
---
Âarch/riscv/include/asm/pgtable.h | 11 +++++++++--
Â1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 06361db3f486..be117a0b4ea1 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -456,8 +456,15 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
Â#define FIXADDR_STARTÂÂÂ (FIXADDR_TOP - FIXADDR_SIZE)

Â/*
- * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32.
- * Note that PGDIR_SIZE must evenly divide TASK_SIZE.
+ * Task size is:
+ * -ÂÂÂÂ 0x9fc00000 (~2.5GB) for RV32.
+ * -ÂÂ 0x4000000000 ( 256GB) for RV64 using SV39 mmu
+ * - 0x800000000000 ( 128TB) for RV64 using SV48 mmu
+ *
+ * Note that PGDIR_SIZE must evenly divide TASK_SIZE since "RISC-V
+ * Instruction Set Manual Volume II: Privileged Architecture" states that
+ * "load and store effective addresses, which are 64bits, must have bits
+ * 63â48 all equal to bit 47, or else a page-fault exception will occur."
 */
Â#ifdef CONFIG_64BIT
Â#define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2)

Reviewed-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx>

Thanks,

Alex