Re: [PATCH v8 00/12] NVIDIA Tegra20 CPUFreq driver major update

From: Thierry Reding
Date: Wed May 06 2020 - 13:05:19 EST


On Thu, Mar 19, 2020 at 10:02:17PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> This series moves intermediate-clk handling from tegra20-cpufreq into
> tegra-clk driver. This allows us to switch to generic cpufreq-dt driver
> which brings voltage scaling, per-hardware OPPs and Tegra30 support out
> of the box. All boards need to adopt CPU OPPs in their device-trees in
> order to get cpufreq support.
>
> Changelog:
>
> v8: - Rebased on a recent linux-next because Thierry merged the cpuidle
> series first and now there is one minor conflict.
>
> - Added tested-by from Nicolas Chauvet who was one of the first
> testers of the series.
>
> v7: - Added acks from Peter De Schrijver.
>
> - Added tested-by from Marcel Ziswiler, Peter Geis, Jasper Korten and
> David Heidelberg who tested these patches on Apalis/Colibri devboards,
> Ouya, TF300T and Nexus 7 devices respectively.
>
> - Rebased series on top of recent linux-next.
>
> v6: - Dropped "cpufreq: dt-platdev: Blacklist NVIDIA Tegra20 and Tegra30 SoCs"
> patch from the series since Viresh picked up that patch separately.
>
> - Added two new patches to this series:
>
> ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
> ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
>
> Previously these patches were sent out separately from this series,
> but it should be more consistent to include them into the series since
> they directly relate to enabling of the cpufreq driver on Tegra30.
>
> v5: - The "Use generic cpufreq-dt driver (Tegra30 supported now)" patch
> is separated now into two patches by factoring out the blacklisting
> of cpufreq-dt-platdev into a standalone patch. This is done in a
> response to request from Jon Hunter to fix the warning splats during
> boot that are coming from OPP core because OPPs are unavailable. The
> OPPs will become available once tegra20-cpufreq driver will be updated
> to support the cpufreq-dt.
>
> v4: - Updated CCLK diagram in the "Add custom CCLK implementation" patch.
>
> - <linux/cpu.h> is now included in the "Use generic cpufreq-dt driver"
> patch, for consistency.
>
> - Returned value of get_cpu_device() is now checked in the "Use generic
> cpufreq-dt driver" patch, for consistency as well.
>
> v3: - The "Add custom CCLK implementation" patch was updated in accordance
> to the comments from Peter De Schrijver. We will not use the clock
> skipper.
>
> - Re added OPPs for T30 Beaver board because Thierry has that board ;)
>
> - Added r-b for the "DT binding" patch from Rob Herring.
>
> v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh Kumar
> in a review comment to v1.
>
> - Added acks from Viresh Kumar.
>
> - Added tested-by from Nicolas Chauvet to the "trimslice" patch.
> Nicolas told me on IRC that it works fine.
>
> - Fixed compilation of the "Add custom CCLK implementation" patch. The
> error happened because v1 was based on top of yet unreviewed/unapplied
> patch "clk: tegra: divider: Support enable-bit for Super clocks".
> Thanks to Peter Geis for reporting the problem.
>
> - Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out
> that's what NVIDIA uses in the testing farm.
>
> Dmitry Osipenko (12):
> clk: tegra: Add custom CCLK implementation
> clk: tegra: pll: Add pre/post rate-change hooks
> clk: tegra: cclk: Add helpers for handling PLLX rate changes
> clk: tegra20: Use custom CCLK implementation
> clk: tegra30: Use custom CCLK implementation

Applied to for-5.8/clk.

> ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
> ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30

Applied to for-5.8/arm/core.

> dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30

Applied to for-5.8/dt-bindings.

> cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported
> now)

Applied to for-5.8/cpufreq.

> ARM: tegra: Create tegra20-cpufreq platform device on Tegra30

Applied to for-5.8/arm/core.

> ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
> ARM: dts: tegra30: beaver: Add CPU Operating Performance Points

Applied to for-5.8/arm/dt.

Thanks,
Thierry

Attachment: signature.asc
Description: PGP signature