[PATCH 0/8] Introduce sv48 support

From: Alexandre Ghiti
Date: Sun May 24 2020 - 05:14:58 EST

This patchset implements sv48 support at runtime. The kernel will try to
boot with 4-level page table and will fallback to 3-level if the HW does not
support it.

The biggest advantage is that we only have one kernel for 64bit, which
is way easier to maintain.

Folding the 4th level into a 3-level page table has almost no cost at
runtime. But as mentioned Palmer, the relocatable code generated is less

At the moment, there is no way to build a 3-level page table non-relocatable
64bit kernel. We agreed that distributions will use this runtime configuration
anyway, but Palmer proposed to introduce a new Kconfig, which I will do later
as sv48 support was asked for 5.8.

Finally, the user can now ask for sv39 explicitly by using the device-tree
which will reduce memory footprint and reduce the number of memory accesses
in case of TLB miss.

Alexandre Ghiti (8):
riscv: Get rid of compile time logic with MAX_EARLY_MAPPING_SIZE
riscv: Allow to dynamically define VA_BITS
riscv: Simplify MAXPHYSMEM config
riscv: Prepare ptdump for vm layout dynamic addresses
riscv: Implement sv48 support
riscv: Allow user to downgrade to sv39 when hw supports sv48
riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo
riscv: Explicit comment about user virtual address space size

arch/riscv/Kconfig | 34 ++--
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 4 -
arch/riscv/include/asm/csr.h | 3 +-
arch/riscv/include/asm/fixmap.h | 1 +
arch/riscv/include/asm/page.h | 15 ++
arch/riscv/include/asm/pgalloc.h | 36 ++++
arch/riscv/include/asm/pgtable-64.h | 97 ++++++++++-
arch/riscv/include/asm/pgtable.h | 30 +++-
arch/riscv/include/asm/sparsemem.h | 2 +-
arch/riscv/kernel/cpu.c | 24 +--
arch/riscv/kernel/head.S | 3 +-
arch/riscv/mm/context.c | 4 +-
arch/riscv/mm/init.c | 194 ++++++++++++++++++---
arch/riscv/mm/ptdump.c | 49 +++++-
14 files changed, 410 insertions(+), 86 deletions(-)