On 5/22/20 1:54 AM, Anup Patel wrote:
On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@xxxxxxxxx> wrote:
On 5/21/20 9:45 AM, Anup Patel wrote:
+- compatible : "sifive,clint-1.0.0" and a string identifying the actual
+ detailed implementation in case that specific bugs need to be worked around.
Should the "riscv,clint0" compatible string be documented here? This
Yes, I forgot to add this compatible string. I will add in v2.
peripheral is not really specific to sifive, as it is present in most
I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and
FPGAs but this IP is only documented as part of SiFive FU540 SOC.
The RISC-V foundation should host the CLINT spec independently
under https://github.com/riscv and make CLINT spec totally open.
For now, I have documented it just like PLIC DT bindings found at:
The PLIC seems to have its own RISC-V-sponsored documentation  which
was split off from the older privileged specs. By your logic above,
should it be renamed to riscv,plic0.txt (with a corresponding change in
the documented compatible strings)?
If RISC-V maintainers agree then I will document it as "RISC-V CLINT".
@Palmer ?? @Paul ??