Re: [PATCH 5/5] dt-bindings: timer: Add CLINT bindings

From: Palmer Dabbelt
Date: Tue May 26 2020 - 20:32:34 EST

On Thu, 21 May 2020 23:29:36 PDT (-0700), seanga2@xxxxxxxxx wrote:
On 5/22/20 1:54 AM, Anup Patel wrote:
On Fri, May 22, 2020 at 1:35 AM Sean Anderson <seanga2@xxxxxxxxx> wrote:

On 5/21/20 9:45 AM, Anup Patel wrote:
+Required properties:
+- compatible : "sifive,clint-1.0.0" and a string identifying the actual
+ detailed implementation in case that specific bugs need to be worked around.

Should the "riscv,clint0" compatible string be documented here? This

Yes, I forgot to add this compatible string. I will add in v2.

peripheral is not really specific to sifive, as it is present in most
rocket-chip cores.

I agree that CLINT is present in a lot of non-SiFive RISC-V SOCs and
FPGAs but this IP is only documented as part of SiFive FU540 SOC.

The RISC-V foundation should host the CLINT spec independently
under and make CLINT spec totally open.

For now, I have documented it just like PLIC DT bindings found at:

The PLIC seems to have its own RISC-V-sponsored documentation [1] which
was split off from the older privileged specs. By your logic above,
should it be renamed to riscv,plic0.txt (with a corresponding change in
the documented compatible strings)?


Let's propose tagging that PLIC spec as v1.0.0 in the platform spec group, but
I don't see a reason why that wouldn't be viable. Assuming that's all OK, we
can start calling this a RISC-V PLIC (in addition to a SiFive PLIC, as they'll
be compatible).

If RISC-V maintainers agree then I will document it as "RISC-V CLINT".

@Palmer ?? @Paul ??

The CLINT is a SiFive spec. It has open source RTL so it's been implemented in
other designs, but it's not a RISC-V spec. The CLIC, which is a superset of
the CLINT, is a RISC-V spec. IIRC it's not finished yet (it's the fast
interrupts task group), but presumably we should have a "riscv,clic-2.0.0" (or
whatever it ends up being called) compat string to go along with the