Re: [PATCH v4 07/15] iommu/vt-d: Delegate the dma domain to upper layer

[Lu Baolu]

Hi Chris,

On 8/24/20 4:35 PM, Chris Wilson wrote:
> Quoting Lu Baolu (2020-08-24 07:31:23)
> > Hi Chris,
> >
> > On 2020/8/22 2:33, Chris Wilson wrote:
> > > Quoting Lu Baolu (2019-05-25 06:41:28)
> > > > This allows the iommu generic layer to allocate a dma domain and
> > > > attach it to a device through the iommu api's. With all types of
> > > > domains being delegated to upper layer, we can remove an internal
> > > > flag which was used to distinguish domains mananged internally or
> > > > externally.
> > >
> > > I'm seeing some really strange behaviour with this patch on a 32b
> > > Skylake system (and still present on mainline). Before this patch
> > > everything is peaceful and appears to work correctly. Applying this patch,
> > > and we fail to initialise the GPU with a few DMAR errors reported, e.g.
> > >
> > > [   20.279445] DMAR: DRHD: handling fault status reg 3
> > > [   20.279508] DMAR: [DMA Read] Request device [00:02.0] fault addr 8900a000 [fault reason 05] PTE Write access is not set
> > >
> > > Setting an identity map for the igfx made the DMAR errors disappear, but
> > > the GPU still failed to initialise.
> > >
> > > There's no difference in the DMAR configuration dmesg between working and
> > > the upset patch. And the really strange part is that switching to a 64b
> > > kernel with this patch, it's working.
> > >
> > > Any suggestions on what I should look for?
> >
> > Can the patch titled "[PATCH] iommu/intel: Handle 36b addressing for
> > x86-32" solve this problem?
>
> It does. Not sure why, but that mystery I can leave for others.

It's caused by left switching 36 bits operation against a 32-bit
integer. Your patch fixes this by converting the integer from unsigned
long to u64. It looks good to me. Thanks!

> -Chris

Best regards,
baolu