RE: [EXT] [RESEND PATCH v3] mtd: spinand: micron: add support for MT29F2G01AAAED

From: Shivamurthy Shastri (sshivamurthy)
Date: Wed Sep 09 2020 - 12:16:32 EST

Next message: Kirill A. Shutemov: "Re: [RFC PATCH 03/16] mm: proc: add 1GB THP kpageflag."
Previous message: Alexander Duyck: "Re: [PATCH v18 00/32] per memcg lru_lock: reviews"
In reply to: Thirumalesha Narasimhappa: "[RESEND PATCH v3] mtd: spinand: micron: add support for MT29F2G01AAAED"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Hi Thirumalesha,

I think it is better to split the patch into two:
1. Changes for the devices which are already present
2. For the device MT29F2G01AAAED, which you want to add

>
> The MT29F2G01AAAED is a single die, 2Gb Micron SPI NAND Flash with 4-bit
> ECC
>
> Signed-off-by: Thirumalesha Narasimhappa <nthirumalesha7@xxxxxxxxx>
> ---
> v3: As per the review comments,
> 1. Renamed read_cache_variants as quadio_read_cache_variants,
> write_cache_variants as
> x4_write_cache_variants/x1_write_cache_variants,
> update_cache_variants as
> x4_update_cache_variants/x1_update_cache_variants,
> read_cache_variants
> as x4_read_cache_variants
> 2. Renamed micron_8_ooblayout as micron_grouped_ooblayout &
> mt29f2g01aaaed_ooblayout as
> micron_interleaved_ooblayout
> 3. Generalized page size based oob section check in
> mt29f2g01aaaed_ooblayout_ecc function
> and separate case check for two bytes BBM reserved in
> mt29f2g01aaaed_ooblayout_free function
> 4. Removed mt29f2g01aaaed_ecc_get_status function &
> MICRON_STATUS_ECC_1TO4_BITFLIPS
>
> v2: removed SPINAND_SELECT_TARGET as per the comments & fixed typo
> errors
>
> drivers/mtd/nand/spi/micron.c | 141 ++++++++++++++++++++++++----------
> 1 file changed, 101 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
> index 5d370cfcdaaa..fa8c20f37611 100644
> --- a/drivers/mtd/nand/spi/micron.c
> +++ b/drivers/mtd/nand/spi/micron.c
> @@ -28,7 +28,7 @@
>
> #define MICRON_SELECT_DIE(x) ((x) << 6)
>
> -static SPINAND_OP_VARIANTS(read_cache_variants,
> +static SPINAND_OP_VARIANTS(quadio_read_cache_variants,
> SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL,
> 0),
> SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL,
> 0),
> @@ -36,14 +36,27 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
> SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
>
> -static SPINAND_OP_VARIANTS(write_cache_variants,
> +static SPINAND_OP_VARIANTS(x4_write_cache_variants,
> SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
> SPINAND_PROG_LOAD(true, 0, NULL, 0));
>
> -static SPINAND_OP_VARIANTS(update_cache_variants,
> +static SPINAND_OP_VARIANTS(x4_update_cache_variants,
> SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
> SPINAND_PROG_LOAD(false, 0, NULL, 0));
>
> +/* Micron MT29F2G01AAAED Device */
> +static SPINAND_OP_VARIANTS(x4_read_cache_variants,
> + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
> + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(x1_write_cache_variants,
> + SPINAND_PROG_LOAD(true, 0, NULL, 0));
> +
> +static SPINAND_OP_VARIANTS(x1_update_cache_variants,
> + SPINAND_PROG_LOAD(false, 0, NULL, 0));
> +
> static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
> struct mtd_oob_region *region)
> {
> @@ -69,11 +82,49 @@ static int micron_8_ooblayout_free(struct mtd_info
> *mtd, int section,
> return 0;
> }
>
> -static const struct mtd_ooblayout_ops micron_8_ooblayout = {
> +static int mt29f2g01aaaed_ooblayout_ecc(struct mtd_info *mtd, int section,
> + struct mtd_oob_region *region)
> +{
> + struct spinand_device *spinand = mtd_to_spinand(mtd);
> +
> + if (section >= spinand->base.memorg.pagesize /
> + mtd->ecc_step_size)
> + return -ERANGE;
> +
> + region->offset = (section * 16) + 8;
> + region->length = 8;
> +
> + return 0;
> +}
> +
> +static int mt29f2g01aaaed_ooblayout_free(struct mtd_info *mtd, int section,
> + struct mtd_oob_region *region)
> +{
> + if (section >= 4)
> + return -ERANGE;

You can deduce the max section with pagesize/ecc_step_size as in the above function.

> +
> + if (section) {
> + region->offset = 16 * section;
> + region->length = 8;
> + } else {
> + /* section 0 has two bytes reserved for the BBM */
> + region->offset = 2;
> + region->length = 6;
> + }
> +
> + return 0;
> +}
> +
> +static const struct mtd_ooblayout_ops micron_grouped_ooblayout = {
> .ecc = micron_8_ooblayout_ecc,
> .free = micron_8_ooblayout_free,
> };
>
> +static const struct mtd_ooblayout_ops micron_interleaved_ooblayout = {
> + .ecc = mt29f2g01aaaed_ooblayout_ecc,
> + .free = mt29f2g01aaaed_ooblayout_free,

I would rename mt29f2g01aaaed_ to a more common one.

> +};
> +
> static int micron_select_target(struct spinand_device *spinand,
> unsigned int target)
> {
> @@ -120,55 +171,55 @@ static const struct spinand_info
> micron_spinand_table[] = {
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
> NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> 0,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status)),
> /* M79A 2Gb 1.8V */
> SPINAND_INFO("MT29F2G01ABBGD",
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
> NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> 0,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status)),
> /* M78A 1Gb 3.3V */
> SPINAND_INFO("MT29F1G01ABAFD",
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
> NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> 0,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status)),
> /* M78A 1Gb 1.8V */
> SPINAND_INFO("MT29F1G01ABAFD",
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
> NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> 0,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status)),
> /* M79A 4Gb 3.3V */
> SPINAND_INFO("MT29F4G01ADAGD",
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
> NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> 0,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status),
> SPINAND_SELECT_TARGET(micron_select_target)),
> /* M70A 4Gb 3.3V */
> @@ -176,33 +227,33 @@ static const struct spinand_info
> micron_spinand_table[] = {
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
> NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> SPINAND_HAS_CR_FEAT_BIT,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status)),
> /* M70A 4Gb 1.8V */
> SPINAND_INFO("MT29F4G01ABBFD",
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
> NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> SPINAND_HAS_CR_FEAT_BIT,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status)),
> /* M70A 8Gb 3.3V */
> SPINAND_INFO("MT29F8G01ADAFD",
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
> NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> SPINAND_HAS_CR_FEAT_BIT,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status),
> SPINAND_SELECT_TARGET(micron_select_target)),
> /* M70A 8Gb 1.8V */
> @@ -210,13 +261,23 @@ static const struct spinand_info
> micron_spinand_table[] = {
>
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
> NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
> NAND_ECCREQ(8, 512),
> - SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
> - &write_cache_variants,
> - &update_cache_variants),
> +
> SPINAND_INFO_OP_VARIANTS(&quadio_read_cache_variants,
> + &x4_write_cache_variants,
> + &x4_update_cache_variants),
> SPINAND_HAS_CR_FEAT_BIT,
> - SPINAND_ECCINFO(&micron_8_ooblayout,
> + SPINAND_ECCINFO(&micron_grouped_ooblayout,
> micron_8_ecc_get_status),
> SPINAND_SELECT_TARGET(micron_select_target)),
> + /* M69A 2Gb 3.3V */
> + SPINAND_INFO("MT29F2G01AAAED",
> +
> SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9F),
> + NAND_MEMORG(1, 2048, 64, 64, 2048, 80, 2, 1, 1),
> + NAND_ECCREQ(4, 512),
> + SPINAND_INFO_OP_VARIANTS(&x4_read_cache_variants,
> + &x1_write_cache_variants,
> + &x1_update_cache_variants),
> + 0,
> + SPINAND_ECCINFO(&micron_interleaved_ooblayout, NULL)),
> };
>
> static int micron_spinand_init(struct spinand_device *spinand)
> --
> 2.17.1

Thanks,
Shiva

Next message: Kirill A. Shutemov: "Re: [RFC PATCH 03/16] mm: proc: add 1GB THP kpageflag."
Previous message: Alexander Duyck: "Re: [PATCH v18 00/32] per memcg lru_lock: reviews"
In reply to: Thirumalesha Narasimhappa: "[RESEND PATCH v3] mtd: spinand: micron: add support for MT29F2G01AAAED"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]