[tip: x86/cpu] x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains

From: tip-bot2 for Krish Sadhukhan
Date: Fri Sep 18 2020 - 05:03:33 EST


The following commit has been merged into the x86/cpu branch of tip:

Commit-ID: 75d1cc0e05af579301ce4e49cf6399be4b4e6e76
Gitweb: https://git.kernel.org/tip/75d1cc0e05af579301ce4e49cf6399be4b4e6e76
Author: Krish Sadhukhan <krish.sadhukhan@xxxxxxxxxx>
AuthorDate: Thu, 17 Sep 2020 21:20:37
Committer: Borislav Petkov <bp@xxxxxxx>
CommitterDate: Fri, 18 Sep 2020 10:47:00 +02:00

x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains

In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page is enforced. In such a
system, it is not required for software to flush the page from all CPU
caches in the system prior to changing the value of the C-bit for the
page. So check that bit before flushing the cache.

[ bp: Massage commit message. ]

Suggested-by: Tom Lendacky <thomas.lendacky@xxxxxxx>
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@xxxxxxxxxx>
Signed-off-by: Borislav Petkov <bp@xxxxxxx>
Link: https://lkml.kernel.org/r/20200917212038.5090-3-krish.sadhukhan@xxxxxxxxxx
---
arch/x86/mm/pat/set_memory.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index d1b2a88..40baa90 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -1999,7 +1999,7 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc)
/*
* Before changing the encryption attribute, we need to flush caches.
*/
- cpa_flush(&cpa, 1);
+ cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT));

ret = __change_page_attr_set_clr(&cpa, 1);