Re: [PATCH v6 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

[Ramuthevar, Vadivel MuruganX]

Hi Linus,

Thank you for the review comments...

On 5/11/2020 3:11 pm, Linus Walleij wrote:
> On Fri, Oct 30, 2020 at 6:32 AM Ramuthevar,Vadivel MuruganX
> <vadivel.muruganx.ramuthevar@xxxxxxxxxxxxxxx> wrote:
>
> > +       ddata  = of_device_get_match_data(dev);
> > +       if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT) {
> > +               if (of_property_read_u32(np, "num-chipselect",
>
> The standard SPI bindings in spi-controller.yaml already has a binding
> for this "num-cs" so please use that. It is also what your device tree
> binding is referencing, 
yes, you are point is valid, I will use that.
so if you were using "num-chipselect" the
> YAML check should give a warning?
In the example, I just converted from existing txt -to- yaml that's
why I didnt face any problem.

Regards
Vadivel
> Yours,
> Linus Walleij