Re: [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance

From: Jonathan Marek
Date: Mon Nov 16 2020 - 12:56:23 EST


On 11/16/20 12:50 PM, Rob Clark wrote:
On Mon, Nov 16, 2020 at 9:33 AM Christoph Hellwig <hch@xxxxxx> wrote:

On Sat, Nov 14, 2020 at 03:07:20PM -0500, Jonathan Marek wrote:
qcom's vulkan driver has nonCoherentAtomSize=1, and it looks like
dma_sync_single_for_cpu() does deal in some way with the partial cache line
case, although I'm not sure that means we can have a nonCoherentAtomSize=1.

No, it doesn't. You need to ensure ownership is managed at
dma_get_cache_alignment() granularity.

my guess is nonCoherentAtomSize=1 only works in the case of cache
coherent buffers


nonCoherentAtomSize doesn't apply to coherent memory (as the name implies), I guess qcom's driver is just wrong about having nonCoherentAtomSize=1.

Jordan just mentioned there is at least one conformance test for this, I wonder if it just doesn't test it well enough, or just doesn't test the non-coherent memory type?