[PATCH v3 2/6] ASoC: audio-graph-card: Add plls and sysclks DT bindings

[Richard Fitzgerald]

The audio-graph-card driver has bindings for configuring the clocking
for DAIs within a component, but is missing bindings for setting
up the PLLs and sysclks of the component.

This patch adds the two new bindings 'plls' and 'sysclks' so that the
audio-graph-driver can fully configure the component clocking.

Signed-off-by: Richard Fitzgerald <rf@xxxxxxxxxxxxxxxxxxxxx>
---
 .../bindings/sound/audio-graph-card.txt       | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/audio-graph-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-card.txt
index d5f6919a2d69..30405e64cfbb 100644
--- a/Documentation/devicetree/bindings/sound/audio-graph-card.txt
+++ b/Documentation/devicetree/bindings/sound/audio-graph-card.txt
@@ -32,6 +32,40 @@ Required properties:
 Optional properties:
 - pa-gpios: GPIO used to control external amplifier.
 
+- plls: A list of component pll settings. There are 4 cells per PLL setting:
+	- phandle to the node of the codec or cpu component,
+	- component PLL id,
+	- component clock source id,
+	- frequency (in Hz) of the PLL output clock.
+
+	The PLL id and clock source id are specific to the particular component
+	so see the relevant component driver for the ids. Typically the
+	clock source id indicates the pin the source clock is connected to.
+
+	The same phandle can appear in multiple entries so that several plls
+	can be set in the same component.
+
+- plls-clocks: A list of clock names giving the source clock for each setting
+	in the plls property.
+
+- sysclks: A list of component sysclk settings.  There are 4 cells per sysclk
+	setting:
+	- phandle to the node of the codec or cpu component,
+	- component sysclk id,
+	- component clock source id,
+	- direction of the clock: 0 if the clock is an input to the component,
+	  1 if it is an output.
+
+	The sysclk id and clock source id are specific to the particular
+	component so see the relevant component driver for the ids. Typically
+	the clock source id indicates the pin the source clock is connected to.
+
+	The same phandle can appear in multiple entries so that several sysclks
+	can be set in the same component.
+
+- sysclks-clocks: A list of clock names giving the source clock for each setting
+	in the sysclks property.
+
 -----------------------
 Example: Single DAI case
 -----------------------
@@ -335,3 +369,41 @@ Example: Multi DAI with DPCM
 			};
 		};
 	};
+
+-----------------------
+Example: Set component sysclks and PLLs
+-----------------------
+
+	sound {
+		compatible = "audio-graph-card";
+
+		clocks = <&audioclk>, <&pll1>;
+		clock-names = "audioclk", "pll1";
+
+		plls = <&cs47l15 MADERA_FLL1_REFCLK MADERA_FLL_SRC_MCLK1 98304000>;
+		plls-clocks = "audioclk";
+
+		sysclks = <&cs47l15 MADERA_CLK_SYSCLK_1 MADERA_CLK_SRC_FLL1 0>;
+		sysclks-clocks = "pll1";
+
+		dais = <&cpu_i2s_port>;
+
+		pll1: pll1 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <98304000>;
+		};
+	};
+
+	cs47l15: codec@0 {
+		...
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cs47l15_aif1_port: port@0 {
+				reg = <0>;
+				cs47l15_aif1: endpoint {
+					remote-endpoint = <&cpu_i2s_endpoint>;
+				};
+			};
+	};
-- 
2.20.1