Re: [PATCH v5] drm/sun4i: tcon: fix inverted DCLK polarity

From: kernel test robot
Date: Wed Jan 13 2021 - 20:42:43 EST

Hi Giulio,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on sunxi/sunxi/for-next]
[also build test ERROR on drm-exynos/exynos-drm-next drm-intel/for-linux-next tegra-drm/drm/tegra/for-next drm-tip/drm-tip v5.11-rc3 next-20210113]
[cannot apply to mripard/sunxi/for-next drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Giulio-Benetti/drm-sun4i-tcon-fix-inverted-DCLK-polarity/20210114-001027
base: https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git sunxi/for-next
config: arm64-randconfig-r005-20210113 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/acbc865cfd67e02cb2e4a37dfd56598eeae38287
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Giulio-Benetti/drm-sun4i-tcon-fix-inverted-DCLK-polarity/20210114-001027
git checkout acbc865cfd67e02cb2e4a37dfd56598eeae38287
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All errors (new ones prefixed by >>):

drivers/gpu/drm/sun4i/sun4i_tcon.c: In function 'sun4i_tcon0_mode_set_rgb':
>> drivers/gpu/drm/sun4i/sun4i_tcon.c:578:7: error: 'SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGDGE' undeclared (first use in this function); did you mean 'SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE'?
578 | SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGDGE |
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE
drivers/gpu/drm/sun4i/sun4i_tcon.c:578:7: note: each undeclared identifier is reported only once for each function it appears in


vim +578 drivers/gpu/drm/sun4i/sun4i_tcon.c

502
503 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
504 const struct drm_encoder *encoder,
505 const struct drm_display_mode *mode)
506 {
507 struct drm_connector *connector = sun4i_tcon_get_connector(encoder);
508 const struct drm_display_info *info = &connector->display_info;
509 unsigned int bp, hsync, vsync;
510 u8 clk_delay;
511 u32 val = 0;
512
513 WARN_ON(!tcon->quirks->has_channel_0);
514
515 tcon->dclk_min_div = tcon->quirks->dclk_min_div;
516 tcon->dclk_max_div = 127;
517 sun4i_tcon0_mode_set_common(tcon, mode);
518
519 /* Set dithering if needed */
520 sun4i_tcon0_mode_set_dithering(tcon, connector);
521
522 /* Adjust clock delay */
523 clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
524 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
525 SUN4I_TCON0_CTL_CLK_DELAY_MASK,
526 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
527
528 /*
529 * This is called a backporch in the register documentation,
530 * but it really is the back porch + hsync
531 */
532 bp = mode->crtc_htotal - mode->crtc_hsync_start;
533 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
534 mode->crtc_htotal, bp);
535
536 /* Set horizontal display timings */
537 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
538 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
539 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
540
541 /*
542 * This is called a backporch in the register documentation,
543 * but it really is the back porch + hsync
544 */
545 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
546 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
547 mode->crtc_vtotal, bp);
548
549 /* Set vertical display timings */
550 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
551 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
552 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
553
554 /* Set Hsync and Vsync length */
555 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
556 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
557 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
558 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
559 SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
560 SUN4I_TCON0_BASIC3_H_SYNC(hsync));
561
562 /* Setup the polarity of the various signals */
563 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
564 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
565
566 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
567 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
568
569 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
570 val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
571
572 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
573 val |= SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE;
574
575 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
576 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
577 SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
> 578 SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGDGE |
579 SUN4I_TCON0_IO_POL_DE_NEGATIVE,
580 val);
581
582 /* Map output pins to channel 0 */
583 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
584 SUN4I_TCON_GCTL_IOMAP_MASK,
585 SUN4I_TCON_GCTL_IOMAP_TCON0);
586
587 /* Enable the output on the pins */
588 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
589 }
590

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip