Re: [PATCH 03/12] perf/x86/intel: Add perf core PMU support for Sapphire Rapids

[Liang, Kan]

On 1/26/2021 9:43 AM, Peter Zijlstra wrote:
> On Tue, Jan 19, 2021 at 12:38:22PM -0800, kan.liang@xxxxxxxxxxxxxxx wrote:
> > @@ -2319,6 +2474,17 @@ static void __icl_update_topdown_event(struct perf_event *event,
> >   {
> >   	u64 delta, last = 0;
> >   
> > +	/*
> > +	 * Although the unsupported topdown events are not exposed to users,
> > +	 * users may mistakenly use the unsupported events via RAW format.
> > +	 * For example, using L2 topdown event, cpu/event=0x00,umask=0x84/,
> > +	 * on Ice Lake. In this case, the scheduler follows the unknown
> > +	 * event handling and assigns a GP counter to the event.
> > +	 * Check the case, and avoid updating unsupported events.
> > +	 */
> > +	if (event->hw.idx < INTEL_PMC_IDX_FIXED)
> > +		return;
> > +
> >   	delta = icl_get_topdown_value(event, slots, metrics);
> >   	if (last_slots)
> >   		last = icl_get_topdown_value(event, last_slots, last_metrics);
>
> Is this a separate patch?

I will move it to a separate patch.

Thanks,
Kan