RE: [PATCH 5.11 079/104] drm/amdgpu: enable only one high prio compute queue

[Deucher, Alexander]

[AMD Public Use]

> -----Original Message-----
> From: Koenig, Christian <Christian.Koenig@xxxxxxx>
> Sent: Friday, March 5, 2021 8:03 AM
> To: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>; linux-
> kernel@xxxxxxxxxxxxxxx
> Cc: stable@xxxxxxxxxxxxxxx; Das, Nirmoy <Nirmoy.Das@xxxxxxx>; Deucher,
> Alexander <Alexander.Deucher@xxxxxxx>; Sasha Levin
> <sashal@xxxxxxxxxx>
> Subject: Re: [PATCH 5.11 079/104] drm/amdgpu: enable only one high prio
> compute queue
> 
> Mhm, I'm not sure this one needs to be backported.
> 
> Why did you pick it up Greg?

It was picked up by Sasha's fixes checker.  

Alex


> 
> Thanks,
> Christian.
> 
> Am 05.03.21 um 13:21 schrieb Greg Kroah-Hartman:
> > From: Nirmoy Das <nirmoy.das@xxxxxxx>
> >
> > [ Upstream commit 8c0225d79273968a65e73a4204fba023ae02714d ]
> >
> > For high priority compute to work properly we need to enable wave
> > limiting on gfx pipe. Wave limiting is done through writing into
> > mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high priority
> > compute queue to avoid race condition between multiple high priority
> > compute queues writing that register simultaneously.
> >
> > Signed-off-by: Nirmoy Das <nirmoy.das@xxxxxxx>
> > Acked-by: Christian König <christian.koenig@xxxxxxx>
> > Reviewed-by: Alex Deucher <alexander.deucher@xxxxxxx>
> > Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> > Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 15 ++++++++-------
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 +-
> >   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  |  6 ++----
> >   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c   |  6 ++----
> >   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   |  7 ++-----
> >   5 files changed, 15 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > index cd2c676a2797..8e0a6c62322e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > @@ -193,15 +193,16 @@ static bool
> amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
> >   }
> >
> >   bool amdgpu_gfx_is_high_priority_compute_queue(struct
> amdgpu_device *adev,
> > -					       int pipe, int queue)
> > +					       struct amdgpu_ring *ring)
> >   {
> > -	bool multipipe_policy = amdgpu_gfx_is_multipipe_capable(adev);
> > -	int cond;
> > -	/* Policy: alternate between normal and high priority */
> > -	cond = multipipe_policy ? pipe : queue;
> > -
> > -	return ((cond % 2) != 0);
> > +	/* Policy: use 1st queue as high priority compute queue if we
> > +	 * have more than one compute queue.
> > +	 */
> > +	if (adev->gfx.num_compute_rings > 1 &&
> > +	    ring == &adev->gfx.compute_ring[0])
> > +		return true;
> >
> > +	return false;
> >   }
> >
> >   void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device
> *adev)
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > index 6b5a8f4642cc..72dbcd2bc6a6 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > @@ -380,7 +380,7 @@ void
> amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int
> bit,
> >   bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
> int mec,
> >   				     int pipe, int queue);
> >   bool amdgpu_gfx_is_high_priority_compute_queue(struct
> amdgpu_device *adev,
> > -					       int pipe, int queue);
> > +					       struct amdgpu_ring *ring);
> >   int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
> >   			       int pipe, int queue);
> >   void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int
> bit,
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index e7d6da05011f..3a291befcddc 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -4495,8 +4495,7 @@ static int gfx_v10_0_compute_ring_init(struct
> amdgpu_device *adev, int ring_id,
> >   	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> >   		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> >   		+ ring->pipe;
> > -	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring->pipe,
> > -							    ring->queue) ?
> > +	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring) ?
> >   			AMDGPU_GFX_PIPE_PRIO_HIGH :
> AMDGPU_GFX_PIPE_PRIO_NORMAL;
> >   	/* type-2 packets are deprecated on MEC, use type-3 instead */
> >   	r = amdgpu_ring_init(adev, ring, 1024, @@ -6545,8 +6544,7 @@ static
> > void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring,
> struct
> >   	struct amdgpu_device *adev = ring->adev;
> >
> >   	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> > -		if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring->pipe,
> > -							      ring->queue)) {
> > +		if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring)) {
> >   			mqd->cp_hqd_pipe_priority =
> AMDGPU_GFX_PIPE_PRIO_HIGH;
> >   			mqd->cp_hqd_queue_priority =
> >
> 	AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > index 37639214cbbb..b0284c4659ba 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -1923,8 +1923,7 @@ static int gfx_v8_0_compute_ring_init(struct
> amdgpu_device *adev, int ring_id,
> >   		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> >   		+ ring->pipe;
> >
> > -	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring->pipe,
> > -							    ring->queue) ?
> > +	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring) ?
> >   			AMDGPU_GFX_PIPE_PRIO_HIGH :
> AMDGPU_RING_PRIO_DEFAULT;
> >   	/* type-2 packets are deprecated on MEC, use type-3 instead */
> >   	r = amdgpu_ring_init(adev, ring, 1024, @@ -4442,8 +4441,7 @@ static
> > void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd
> *m
> >   	struct amdgpu_device *adev = ring->adev;
> >
> >   	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> > -		if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring->pipe,
> > -							      ring->queue)) {
> > +		if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring)) {
> >   			mqd->cp_hqd_pipe_priority =
> AMDGPU_GFX_PIPE_PRIO_HIGH;
> >   			mqd->cp_hqd_queue_priority =
> >
> 	AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 5f4805e4d04a..3e800193a604 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -2228,8 +2228,7 @@ static int gfx_v9_0_compute_ring_init(struct
> amdgpu_device *adev, int ring_id,
> >   	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
> >   		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
> >   		+ ring->pipe;
> > -	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring->pipe,
> > -							    ring->queue) ?
> > +	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring) ?
> >   			AMDGPU_GFX_PIPE_PRIO_HIGH :
> AMDGPU_GFX_PIPE_PRIO_NORMAL;
> >   	/* type-2 packets are deprecated on MEC, use type-3 instead */
> >   	return amdgpu_ring_init(adev, ring, 1024, @@ -3391,9 +3390,7 @@
> > static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct
> v9_mqd *m
> >   	struct amdgpu_device *adev = ring->adev;
> >
> >   	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> > -		if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> > -							      ring->pipe,
> > -							      ring->queue)) {
> > +		if (amdgpu_gfx_is_high_priority_compute_queue(adev,
> ring)) {
> >   			mqd->cp_hqd_pipe_priority =
> AMDGPU_GFX_PIPE_PRIO_HIGH;
> >   			mqd->cp_hqd_queue_priority =
> >
> 	AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;