Re: [PATCH v4 01/16] perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers

[Xu, Like]

Hi Xiangdong,

On 2021/4/6 11:24, Liuxiangdong (Aven, Cloud Infrastructure Service Product 
Dept.) wrote:
> Hi，like.
> Some questions about this new pebs patches set：
> https://lore.kernel.org/kvm/20210329054137.120994-2-like.xu@xxxxxxxxxxxxxxx/
>
> The new hardware facility supporting guest PEBS is only available
> on Intel Ice Lake Server platforms for now.

Yes, we have documented this "EPT-friendly PEBS" capability in the SDM
18.3.10.1 Processor Event Based Sampling (PEBS) Facility

And again, this patch set doesn't officially support guest PEBS on the Skylake.

> AFAIK， Icelake supports adaptive PEBS and extended PEBS which Skylake 
> doesn't.
> But we can still use IA32_PEBS_ENABLE MSR to indicate general-purpose 
> counter in Skylake.

For Skylake, only the PMC0-PMC3 are valid for PEBS and you may
mask the other unsupported bits in the pmu->pebs_enable_mask.

> Is there anything else that only Icelake supports in this patches set?

The PDIR counter on the Ice Lake is the fixed counter 0
while the PDIR counter on the Sky Lake is the gp counter 1.

You may also expose x86_pmu.pebs_vmx for Skylake in the 1st patch.

> Besides, we have tried this patches set in Icelake.  We can use pebs(eg: 
> "perf record -e cycles:pp")
> when guest is kernel-5.11, but can't when kernel-4.18.  Is there a 
> minimum guest kernel version requirement?

The Ice Lake CPU model has been added since v5.4.

You may double check whether the stable tree(s) code has
INTEL_FAM6_ICELAKE in the arch/x86/include/asm/intel-family.h.

> Thanks,
> Xiangdong Liu