Re: [PATCH v4 01/16] perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers

[Liuxiangdong (Aven, Cloud Infrastructure Service Product Dept.)]

On 2021/4/6 13:14, Xu, Like wrote:
> Hi Xiangdong,
>
> On 2021/4/6 11:24, Liuxiangdong (Aven, Cloud Infrastructure Service 
> Product Dept.) wrote:
> > Hi，like.
> > Some questions about this new pebs patches set：
> > https://lore.kernel.org/kvm/20210329054137.120994-2-like.xu@xxxxxxxxxxxxxxx/ 
> >
> >
> > The new hardware facility supporting guest PEBS is only available
> > on Intel Ice Lake Server platforms for now.
>
> Yes, we have documented this "EPT-friendly PEBS" capability in the SDM
> 18.3.10.1 Processor Event Based Sampling (PEBS) Facility
>
> And again, this patch set doesn't officially support guest PEBS on the 
> Skylake.
>
> > AFAIK， Icelake supports adaptive PEBS and extended PEBS which 
> > Skylake doesn't.
> > But we can still use IA32_PEBS_ENABLE MSR to indicate general-purpose 
> > counter in Skylake.
>
> For Skylake, only the PMC0-PMC3 are valid for PEBS and you may
> mask the other unsupported bits in the pmu->pebs_enable_mask.
>
> > Is there anything else that only Icelake supports in this patches set?
>
> The PDIR counter on the Ice Lake is the fixed counter 0
> while the PDIR counter on the Sky Lake is the gp counter 1.
>
> You may also expose x86_pmu.pebs_vmx for Skylake in the 1st patch.

Yes. In fact, I have tried using this patch set in Skylake after these 
modifications:
1.  Expose x86_pmu.pebs_vmx for Skylake.
2.  Use PMC0-PMC3 for pebs
    2.1 Replace "INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed" with 
"x86_pmu.max_pebs_events" in "x86_pmu_handle_guest_pebs"
    2.2 Unmask other unsupported bits in the pmu->pebs_enable_mask. 
IA32_PERF_CAPABILITIES.PEBS_BASELINE [bit 14]
          is always 0 in Skylake, so pmu->pebs_enable_mask equals 
`((1ull << pmu->nr_arch_gp_counters)-1).
    2.3  Replace "pmc->idx == 32 " with "pmc->idx == 1" because the 
PDIR counter on the Skylake is the gp counter 1.
3.  Shield patch-09 because Skylake does not support adaptive pebs.
4.  Shield all cpu check code in this patch set just for test.


But, unfortunately, guest will record only a few seconds and then host 
will certainly soft lockup .
Is there anything wrong?

> > Besides, we have tried this patches set in Icelake.  We can use 
> > pebs(eg: "perf record -e cycles:pp")
> > when guest is kernel-5.11, but can't when kernel-4.18.  Is there a 
> > minimum guest kernel version requirement?
>
> The Ice Lake CPU model has been added since v5.4.
>
> You may double check whether the stable tree(s) code has
> INTEL_FAM6_ICELAKE in the arch/x86/include/asm/intel-family.h.
>
> > Thanks,
> > Xiangdong Liu