Re: [PATCH 1/2] dt-bindings: pwm: add bindings for PWM modules inside QCOM PMICs

[Thierry Reding]

On Tue, Apr 27, 2021 at 06:22:09PM +0800, Fenglin Wu wrote:
> Add bindings for QCOM PMIC PWM modules which are accessed through SPMI
> bus.
> 
> Signed-off-by: Fenglin Wu <fenglinw@xxxxxxxxxxxxxx>
> ---
>  .../devicetree/bindings/pwm/pwm-qcom.yaml          | 51 ++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-qcom.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-qcom.yaml b/Documentation/devicetree/bindings/pwm/pwm-qcom.yaml
> new file mode 100644
> index 0000000..e8d8ed6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/pwm-qcom.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/pwm-qcom.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. PMIC PWM bindings
> +
> +maintainers:
> +  - Fenglin Wu <fenglinw@xxxxxxxxxxxxxx>
> +
> +description:
> +  PWM modules inside Qualcomm Technologies, Inc. PMICs can be accessed through
> +  SPMI bus and normally one PMIC would have multiple PWM modules with adjacent
> +  SPMI address space.
> +
> +Properties:
> +  compatible:
> +    const: qcom,pwm

This seems a bit vague. What if Qualcomm ever designs a different PWM?
How are you going to tell them apart? Typically this would include some
sort of ID for the SoC family, or the first SoC that this was introduced
on. That way you can more easily distinguish between different designs
later on.

> +
> +  reg:
> +    description:
> +      The SPMI address base of the PWM module, if there are multiple PWM
> +      modules present with adjacent SPMI address space, only need to specify
> +      the address base of the 1st PWM module.

That seems like an odd way to define these. It looks like this is a bus
with #address-cells = <1> and #size-cells = <0>. Such busses are usually
assumed to have a single address per device (see for example I2C). How
does the SPMI addressing work? Is there a specification somewhere?

Actually, Documentation/devicetree/bindings/spmi/spmi.yaml says that
SPMI child devices should have two address cells, so this seesm to be at
odds with that specification.

Thierry

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