Re: [PATCH v5 2/3] sched/topology: Rework CPU capacity asymmetry detection

[Beata Michalska]

On Thu, May 27, 2021 at 05:08:42PM +0200, Dietmar Eggemann wrote:
> On 26/05/2021 23:40, Beata Michalska wrote:
> > On Wed, May 26, 2021 at 08:17:41PM +0200, Dietmar Eggemann wrote:
> >> On 26/05/2021 14:51, Beata Michalska wrote:
> >>> On Wed, May 26, 2021 at 01:15:46PM +0100, Beata Michalska wrote:
> >>>> On Wed, May 26, 2021 at 11:52:25AM +0200, Dietmar Eggemann wrote:
> >>>>> On 25/05/2021 12:29, Beata Michalska wrote:
> >>>>>> On Tue, May 25, 2021 at 10:53:07AM +0100, Valentin Schneider wrote:
> >>>>>>> On 24/05/21 23:55, Beata Michalska wrote:
> >>>>>>>> On Mon, May 24, 2021 at 07:01:04PM +0100, Valentin Schneider wrote:
> >>>>>>>>> On 24/05/21 11:16, Beata Michalska wrote:
> 
> [...]
> 
> >>                 cpu-map {
> >>                         cluster0 {
> >>                                 core0 {
> >> 					thread0 {
> >>                                         	cpu = <&A53_0>;
> >> 					};
> >> 					thread1 {
> >>                                         	cpu = <&A53_1>;
> >> 					};
> >>                                 };
> >>                                 core1 {
> >> 					thread0 {
> >>                                         	cpu = <&A53_2>;
> >> 					};
> >> 					thread1 {
> >>                                         	cpu = <&A53_3>;
> >> 					};
> >>                                 };
> >>                                 core2 {
> >> 					thread0 {
> >>                                         	cpu = <&A53_4>;
> >> 					};
> >> 					thread1 {
> >>                                         	cpu = <&A53_5>;
> >> 					};
> >>                                 };
> >>                         };
> >>
> >>                         cluster1 {
> >>                                 core0 {
> >> 					thread0 {
> >>                                         	cpu = <&A53_6>;
> >> 					};
> >> 					thread1 {
> >>                                         	cpu = <&A53_7>;
> >> 					};
> >>                                 };
> >>                         };
> >>                 };
> >>
> >> 		A53_0: cpu@0 {
> >> 			capacity-dmips-mhz = <446>;
> >> 	 	A53_1: cpu@1 {
> >> 			capacity-dmips-mhz = <1024>;
> >> 		A53_2: cpu@2 {
> >> 			capacity-dmips-mhz = <871>;
> >> 		A53_3: cpu@3 {
> >> 			capacity-dmips-mhz = <1024>;
> >> 		A53_4: cpu@4 {
> >> 			capacity-dmips-mhz = <446>;
> >> 		A53_5: cpu@5 {
> >> 			capacity-dmips-mhz = <871>;
> >> 		A53_6: cpu@6 {
> >> 			capacity-dmips-mhz = <1024>;
> >> 		A53_7: cpu@7 {
> >> 			capacity-dmips-mhz = <1024>;
> >>
> >> Here I guess SD_ASYM_CPUCAPACITY will be attached to SMT[0-5]. So this
> >> 'capacity-dmips-mhz' config error won't be detected.
> >>
> >> In case all CPUs (i.e. hw threads would have the correct
> >> capacity-dmips-mhz = <1024> or not being set (default 1024))
> >> asym_cap_list would corrcetly only have 1 entry.
> > We could possibly add a warning (like in EAS) if the asymmetry is detected
> > for SMT which would give some indication that there is smth ... wrong ?
> 
> Maybe, in case you find an easy way to detect this.
> 
> But the issue already exists today. Not with the topology mentioned
> above but in case we slightly change it to:
> 
>   cpus = { ([446 1024] [871 1024] [446 1024] ) ([1024 1024]) }
>                                        ^^^^
> so that we have a 1024 CPU in the lowest sd for each CPU, we would get
> SD_ASYM_CPUCAPACITY on SMT.
The asymmetry capacity flags are being set on a sched domain level, so
we could use the SD_SHARE_CPUCAPACITY|SD_SHARE_PKG_RESOURCES (cpu_smt_flags)
flags to determine if having asymmetry is valid or not ? If this is enough 
this could be handled by the classify function?

---
BR
B.