[PATCH v6 1/3] dt-bindings: dma: add schema for altera-msgdma

[Olivier Dautricourt]

add yaml schema for Altera mSGDMA bindings in devicetree.

Reviewed-by: Stefan Roese <sr@xxxxxxx>
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Olivier Dautricourt <olivier.dautricourt@xxxxxxxxxx>
---

Notes:
    Changes in v2:
     - fix reg size in dt example
     - fix dt_binding check warning
     - add list in MAINTAINERS entry

    Changes from v2 to v3:
     none

    Changes from v3 to v4:
     none

    Changes from v4 to v5:
        as per Rob's comments:
            - change compatible field from 'altr,msgdma' to
              'altr,socfpga-msgdma' to indicate that it's compatible
               with altera socfpga family.
            - describe each region separately
            - remove maxItems/minItems for reg section.
        as per Vinod's comments:
            - separate MAINTAINERS editing in another commit
            - remove description for #dma-cells
    v6:
      add description for the unique dma cell (channel id must be 0)

 .../devicetree/bindings/dma/altr,msgdma.yaml  | 61 +++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/altr,msgdma.yaml

diff --git a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml
new file mode 100644
index 000000000000..a4f9fe23dcd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera mSGDMA IP core
+
+maintainers:
+  - Olivier Dautricourt <olivier.dautricourt@xxxxxxxxxx>
+
+description: |
+  Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
+  intellectual property (IP)
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  compatible:
+    const: altr,socfpga-msgdma
+
+  reg:
+    items:
+      - description: Control and Status Register Slave Port
+      - description: Descriptor Slave Port
+      - description: Response Slave Port
+
+  reg-names:
+    items:
+      - const: csr
+      - const: desc
+      - const: resp
+
+  interrupts:
+    maxItems: 1
+
+  "#dma-cells":
+    const: 1
+    description:
+      The cell identifies the channel id (must be 0)
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    msgdma_controller: dma-controller@ff200b00 {
+        compatible = "altr,socfpga-msgdma";
+        reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
+        reg-names = "csr", "desc", "resp";
+        interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+        #dma-cells = <1>;
+    };
--
2.31.0.rc2


--
Olivier Dautricourt