Re: [PATCH 7/8] membarrier: Remove arm (32) support for SYNC_CORE

[Russell King (Oracle)]

On Wed, Jun 16, 2021 at 05:00:51PM +0100, Catalin Marinas wrote:
> On Wed, Jun 16, 2021 at 04:45:29PM +0100, Catalin Marinas wrote:
> > On Wed, Jun 16, 2021 at 04:23:26PM +0100, Russell King wrote:
> > > On Wed, Jun 16, 2021 at 04:04:56PM +0100, Catalin Marinas wrote:
> > > > The simpler fix for flush_icache_range() is to disable preemption, read
> > > > a word in a cacheline to force any dirty lines on another CPU to be
> > > > evicted and then issue the D-cache maintenance (for those cache lines
> > > > which are still dirty on the current CPU).
> > > 
> > > Is just reading sufficient? If so, why do we do a read-then-write in
> > > the MPCore DMA cache ops? Don't we need the write to force exclusive
> > > ownership? If we don't have exclusive ownership of the dirty line,
> > > how can we be sure to write it out of the caches?
> > 
> > For cleaning (which is the case for I/D coherency), we only need reading
> > since we are fine with clean lines being left in the D-cache on other
> > CPUs. For invalidation, we indeed need to force the exclusive ownership,
> > hence the write.
> 
> Ah, I'm not sure the I-cache is broadcast in hardware on ARM11MPCore
> either. So fixing the D side won't be sufficient.

The other question is... do we bother to fix this.

Arnd tells me that the current remaining ARM11MPCore users are:
- CNS3xxx (where there is some martinal interest in the Gateworks
  Laguna platform)
- Similar for OXNAS
- There used to be the Realview MPCore tile - I haven't turned that on
  in ages, and it may be that the 3V cell that backs up the encryption
  keys is dead so it may not even boot.
- Not sure about the story with QEMU - Arnd doesn't think there would
  be a problem there as it may not model caches.

So it seems to come down to a question about CNS3xxx and OXNAS. If
these aren't being used, maybe we can drop ARM11MPCore support and
the associated platforms?

Linus, Krzysztof, Neil, any input?

Thanks.

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