[PATCH v5 00/13] Introduce Architectural LBR for vPMU

From: Yang Weijiang
Date: Fri Jul 09 2021 - 05:51:06 EST


The Architectural Last Branch Records (LBRs) is published in the 319433-040
release of Intel Architecture Instruction Set Extensions and Future Features
Programming Reference[0].

The main advantages of Arch LBR are [1]:
- Faster context switching due to XSAVES support and faster reset of
LBR MSRs via the new DEPTH MSR
- Faster LBR read for a non-PEBS event due to XSAVES support, which
lowers the overhead of the NMI handler.
- Linux kernel can support the LBR features without knowing the model
number of the current CPU.

>From end user's point of view, the usage of Arch LBR is the same as
the Legacy LBR that has been merged in the mainline.

[0] https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-and-future-features-programming-reference.html
[1] https://lore.kernel.org/lkml/1593780569-62993-1-git-send-email-kan.liang@xxxxxxxxxxxxxxx/

Note: to make the patchset buildable with kernel tree, this series includes 3 queued
CET patches from Paolo's queued branch.

Previous version:
v4:
https://lkml.kernel.org/kvm/20210510081535.94184-1-like.xu@xxxxxxxxxxxxxxx/

Like Xu (6):
perf/x86/intel: Fix the comment about guest LBR support on KVM
perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers
KVM: vmx/pmu: Emulate MSR_ARCH_LBR_DEPTH for guest Arch LBR
KVM: vmx/pmu: Emulate MSR_ARCH_LBR_CTL for guest Arch LBR
KVM: x86: Refine the matching and clearing logic for supported_xss
KVM: x86: Add XSAVE Support for Architectural LBR

Sean Christopherson (1):
KVM: x86: Report XSS as an MSR to be saved if there are supported
features

Yang Weijiang (6):
KVM: x86: Add arch LBR MSRs to msrs_to_save_all list
KVM: x86/vmx: Save/Restore host MSR_ARCH_LBR_CTL state
KVM: x86/pmu: Refactor code to support guest Arch LBR
KVM: x86: Refresh CPUID on writes to MSR_IA32_XSS
KVM: x86/vmx: Check Arch LBR config when return perf capabilities
KVM: x86/cpuid: Advise Arch LBR feature in CPUID

arch/x86/events/intel/core.c | 3 +-
arch/x86/events/intel/lbr.c | 6 +-
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/include/asm/vmx.h | 4 ++
arch/x86/kvm/cpuid.c | 44 ++++++++++--
arch/x86/kvm/vmx/capabilities.h | 25 ++++---
arch/x86/kvm/vmx/pmu_intel.c | 114 +++++++++++++++++++++++++++----
arch/x86/kvm/vmx/vmx.c | 50 ++++++++++++--
arch/x86/kvm/vmx/vmx.h | 4 ++
arch/x86/kvm/x86.c | 24 ++++++-
11 files changed, 237 insertions(+), 39 deletions(-)

--
2.21.1