[PATCH 4.19 323/421] tty: serial: fsl_lpuart: fix the potential risk of division or modulo by zero

From: Greg Kroah-Hartman
Date: Mon Jul 19 2021 - 12:32:52 EST

From: Sherry Sun <sherry.sun@xxxxxxx>

[ Upstream commit fcb10ee27fb91b25b68d7745db9817ecea9f1038 ]

We should be very careful about the register values that will be used
for division or modulo operations, althrough the possibility that the
UARTBAUD register value is zero is very low, but we had better to deal
with the "bad data" of hardware in advance to avoid division or modulo
by zero leading to undefined kernel behavior.

Signed-off-by: Sherry Sun <sherry.sun@xxxxxxx>
Link: https://lore.kernel.org/r/20210427021226.27468-1-sherry.sun@xxxxxxx
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
drivers/tty/serial/fsl_lpuart.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 4b9f42269477..deb9d4fa9cb0 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -1992,6 +1992,9 @@ lpuart32_console_get_options(struct lpuart_port *sport, int *baud,

bd = lpuart32_read(&sport->port, UARTBAUD);
+ if (!bd)
+ return;
sbr = bd;
uartclk = clk_get_rate(sport->clk);