[PATCH 5.13 142/156] ARM: dts: everest: Add phase corrections for eMMC

From: Greg Kroah-Hartman
Date: Thu Jul 22 2021 - 12:54:23 EST

From: Andrew Jeffery <andrew@xxxxxxxx>

commit faffd1b2bde3ee428d6891961f6a60f8e08749d6 upstream.

The values were determined experimentally via boot tests, not by
measuring the bus behaviour with a scope. We plan to do scope
measurements to confirm or refine the values and will update the
devicetree if necessary once these have been obtained.

However, with the patch we can write and read data without issue, where
as booting the system without the patch failed at the point of mounting
the rootfs.

Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx>
Link: https://lore.kernel.org/r/20210628013605.1257346-1-andrew@xxxxxxxx
Fixes: 2fc88f92359d ("mmc: sdhci-of-aspeed: Expose clock phase controls")
Fixes: a5c5168478d7 ("ARM: dts: aspeed: Add Everest BMC machine")
Signed-off-by: Joel Stanley <joel@xxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 1 +
1 file changed, 1 insertion(+)

--- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
@@ -1068,6 +1068,7 @@

&emmc {
status = "okay";
+ clk-phase-mmc-hs200 = <180>, <180>;

&fsim0 {