Re: [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data

From: Stephen Boyd
Date: Tue Jul 27 2021 - 13:55:05 EST

Quoting Chun-Jie Chen (2021-07-26 03:57:05)
> In all MediaTek PLL design, bit0 of CON0 register is always
> the enable bit.
> However, there's a special case of usbpll on MT8192.
> The enable bit of usbpll is moved to bit2 of other register.
> Add configurable en_reg and pll_en_bit for enable control or
> default 0 where pll data are static variables.
> Hence, CON0_BASE_EN could also be removed.
> And there might have another special case on other chips,
> the enable bit is still on CON0 register but not at bit0.
> Reviewed-by: Ikjoon Jang <ikjn@xxxxxxxxxxxx>
> Signed-off-by: Weiyi Lu <>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@xxxxxxxxxxxx>
> ---

Applied to clk-next