Re: [PATCH v3 02/13] ARM: dts: sti: update flexgen compatible within stih407-clock

[Patrice CHOTARD]

Hi Alain

On 3/31/21 10:42 PM, Alain Volmat wrote:
> With the introduction of new flexgen compatible within the clk-flexgen
> driver, remove the clock-output-names entry from the flexgen nodes
> and set the new proper compatible corresponding.
> 
> Signed-off-by: Alain Volmat <avolmat@xxxxxx>
> ---
>  arch/arm/boot/dts/stih407-clock.dtsi | 85 ++--------------------------
>  1 file changed, 6 insertions(+), 79 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
> index 1ab40db7c91a..ecd568777e5f 100644
> --- a/arch/arm/boot/dts/stih407-clock.dtsi
> +++ b/arch/arm/boot/dts/stih407-clock.dtsi
> @@ -83,15 +83,12 @@
>  			};
>  
>  			clk_s_a0_flexgen: clk-s-a0-flexgen {
> -				compatible = "st,flexgen";
> +				compatible = "st,flexgen", "st,flexgen-stih407-a0";
>  
>  				#clock-cells = <1>;
>  
>  				clocks = <&clk_s_a0_pll 0>,
>  					 <&clk_sysin>;
> -
> -				clock-output-names = "clk-ic-lmi0";
> -				clock-critical = <CLK_IC_LMI0>;
>  			};
>  		};
>  
> @@ -134,7 +131,7 @@
>  
>  			clk_s_c0_flexgen: clk-s-c0-flexgen {
>  				#clock-cells = <1>;
> -				compatible = "st,flexgen";
> +				compatible = "st,flexgen", "st,flexgen-stih407-c0";
>  
>  				clocks = <&clk_s_c0_pll0 0>,
>  					 <&clk_s_c0_pll1 0>,
> @@ -144,45 +141,6 @@
>  					 <&clk_s_c0_quadfs 3>,
>  					 <&clk_sysin>;
>  
> -				clock-output-names = "clk-icn-gpu",
> -						     "clk-fdma",
> -						     "clk-nand",
> -						     "clk-hva",
> -						     "clk-proc-stfe",
> -						     "clk-proc-tp",
> -						     "clk-rx-icn-dmu",
> -						     "clk-rx-icn-hva",
> -						     "clk-icn-cpu",
> -						     "clk-tx-icn-dmu",
> -						     "clk-mmc-0",
> -						     "clk-mmc-1",
> -						     "clk-jpegdec",
> -						     "clk-ext2fa9",
> -						     "clk-ic-bdisp-0",
> -						     "clk-ic-bdisp-1",
> -						     "clk-pp-dmu",
> -						     "clk-vid-dmu",
> -						     "clk-dss-lpc",
> -						     "clk-st231-aud-0",
> -						     "clk-st231-gp-1",
> -						     "clk-st231-dmu",
> -						     "clk-icn-lmi",
> -						     "clk-tx-icn-disp-1",
> -						     "clk-icn-sbc",
> -						     "clk-stfe-frc2",
> -						     "clk-eth-phy",
> -						     "clk-eth-ref-phyclk",
> -						     "clk-flash-promip",
> -						     "clk-main-disp",
> -						     "clk-aux-disp",
> -						     "clk-compo-dvp";
> -				clock-critical = <CLK_PROC_STFE>,
> -						 <CLK_ICN_CPU>,
> -						 <CLK_TX_ICN_DMU>,
> -						 <CLK_EXT2F_A9>,
> -						 <CLK_ICN_LMI>,
> -						 <CLK_ICN_SBC>;
> -
>  				/*
>  				 * ARM Peripheral clock for timers
>  				 */
> @@ -219,18 +177,13 @@
>  
>  			clk_s_d0_flexgen: clk-s-d0-flexgen {
>  				#clock-cells = <1>;
> -				compatible = "st,flexgen-audio", "st,flexgen";
> +				compatible = "st,flexgen", "st,flexgen-stih407-d0";
>  
>  				clocks = <&clk_s_d0_quadfs 0>,
>  					 <&clk_s_d0_quadfs 1>,
>  					 <&clk_s_d0_quadfs 2>,
>  					 <&clk_s_d0_quadfs 3>,
>  					 <&clk_sysin>;
> -
> -				clock-output-names = "clk-pcm-0",
> -						     "clk-pcm-1",
> -						     "clk-pcm-2",
> -						     "clk-spdiff";
>  			};
>  		};
>  
> @@ -253,7 +206,7 @@
>  
>  			clk_s_d2_flexgen: clk-s-d2-flexgen {
>  				#clock-cells = <1>;
> -				compatible = "st,flexgen-video", "st,flexgen";
> +				compatible = "st,flexgen", "st,flexgen-stih407-d2";
>  
>  				clocks = <&clk_s_d2_quadfs 0>,
>  					 <&clk_s_d2_quadfs 1>,
> @@ -262,24 +215,7 @@
>  					 <&clk_sysin>,
>  					 <&clk_sysin>,
>  					 <&clk_tmdsout_hdmi>;
> -
> -				clock-output-names = "clk-pix-main-disp",
> -						     "clk-pix-pip",
> -						     "clk-pix-gdp1",
> -						     "clk-pix-gdp2",
> -						     "clk-pix-gdp3",
> -						     "clk-pix-gdp4",
> -						     "clk-pix-aux-disp",
> -						     "clk-denc",
> -						     "clk-pix-hddac",
> -						     "clk-hddac",
> -						     "clk-sddac",
> -						     "clk-pix-dvo",
> -						     "clk-dvo",
> -						     "clk-pix-hdmi",
> -						     "clk-tmds-hdmi",
> -						     "clk-ref-hdmiphy";
> -						     };
> +			};
>  		};
>  
>  		clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
> @@ -301,22 +237,13 @@
>  
>  			clk_s_d3_flexgen: clk-s-d3-flexgen {
>  				#clock-cells = <1>;
> -				compatible = "st,flexgen";
> +				compatible = "st,flexgen", "st,flexgen-stih407-d3";
>  
>  				clocks = <&clk_s_d3_quadfs 0>,
>  					 <&clk_s_d3_quadfs 1>,
>  					 <&clk_s_d3_quadfs 2>,
>  					 <&clk_s_d3_quadfs 3>,
>  					 <&clk_sysin>;
> -
> -				clock-output-names = "clk-stfe-frc1",
> -						     "clk-tsout-0",
> -						     "clk-tsout-1",
> -						     "clk-mchi",
> -						     "clk-vsens-compo",
> -						     "clk-frc1-remote",
> -						     "clk-lpc-0",
> -						     "clk-lpc-1";
>  			};
>  		};
>  	};
> 

Reviewed-by: Patrice Chotard <patrice.chotard@xxxxxxxxxxx>

Thanks
Patrice