Re: [PATCH v3 2/3] KVM: x86: Handle the case of 5-level shadow page table
From: Paolo Bonzini
Date: Thu Aug 19 2021 - 12:36:22 EST
On 18/08/21 19:15, Sean Christopherson wrote:
When the 5-level page table CPU flag is exposed, KVM code needs to handle
Similarly, this is wrong, or maybe just poorly worded. This has nothing to do
this case by pointing mmu->root_hpa to a properly-constructed 5-level page
with LA57 being exposed to the guest, it's purely the host using 5-level paging
and NPT being enabled and exposed to L1.
KVM: x86/mmu: Support shadowing NPT when 5-level paging is enabled in host
When the 5-level page table CPU flag is set in the host, but the guest
has CR4.LA57=0 (including the case of a 32-bit guest), the top level of
the shadow NPT page tables will be fixed, consisting of one pointer to
a lower-level table and 511 non-present entries. Extend the existing
code that creates the fixed PML4 or PDP table, to provide a fixed PML5
table if needed.
This is not needed on EPT because the number of layers in the tables
is specified in the EPTP instead of depending on the host CR4.