RE: [PATCH v2] arm64: dts: qcom: sc7280: Add WPSS remoteproc node

From: pillair
Date: Thu Sep 09 2021 - 04:39:03 EST




> -----Original Message-----
> From: Stephen Boyd <swboyd@xxxxxxxxxxxx>
> Sent: Wednesday, August 11, 2021 1:22 AM
> To: Rakesh Pillai <pillair@xxxxxxxxxxxxxx>; agross@xxxxxxxxxx;
> bjorn.andersson@xxxxxxxxxx; robh+dt@xxxxxxxxxx
> Cc: linux-arm-msm@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; sibis@xxxxxxxxxxxxxx; mpubbise@xxxxxxxxxxxxxx
> Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Add WPSS remoteproc
> node
>
> Quoting Rakesh Pillai (2021-08-10 11:11:29)
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 53a21d0..41a7826 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -74,6 +74,16 @@
> > reg = <0 0x8b700000 0 0x10000>;
> > no-map;
> > };
> > +
> > + wlan_fw_mem: memory@80c00000 {
> > + no-map;
> > + reg = <0x0 0x80c00000 0x0 0xc00000>;
> > + };
>
> Please try to keep this sorted by reg address. 80c00000 comes before
> 8b700000.
>

Hi Stephen,
I will fix this and send v3 for this patch.


> > +
> > + wpss_mem: memory@9ae00000 {
> > + no-map;
> > + reg = <0x0 0x9ae00000 0x0 0x1900000>;
> > + };
> > };
> >
> > cpus {
> > @@ -1270,6 +1280,53 @@
> > };
> > };
> >
> > + remoteproc_wpss: remoteproc@8a00000 {
> > + compatible = "qcom,sc7280-wpss-pil";
> > + reg = <0 0x08a00000 0 0x10000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 587
> IRQ_TYPE_EDGE_RISING>,
> > + <&wpss_smp2p_in 0 IRQ_TYPE_NONE>,
> > + <&wpss_smp2p_in 1 IRQ_TYPE_NONE>,
> > + <&wpss_smp2p_in 2 IRQ_TYPE_NONE>,
> > + <&wpss_smp2p_in 3 IRQ_TYPE_NONE>,
> > + <&wpss_smp2p_in 7
> > + IRQ_TYPE_NONE>;
>
> Is this IRQ_TYPE_EDGE_RISING? Please add some type of edge or level flag.

I will change it to IRQ_TYPE_EDGE_RISING and send out the next revision.

>
> > + interrupt-names = "wdog", "fatal", "ready", "handover",
> > + "stop-ack", "shutdown-ack";
> > +
> > + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
> > + <&gcc GCC_WPSS_AHB_CLK>,
> > + <&gcc GCC_WPSS_RSCP_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>;
> > + clock-names = "gcc_wpss_ahb_bdg_mst_clk",
> > + "gcc_wpss_ahb_clk",
> > + "gcc_wpss_rscp_clk",
> > + "xo";
> > +
> > + memory-region = <&wpss_mem>;
> > +
> > + qcom,smem-states = <&wpss_smp2p_out 0>;