[tip: perf/core] perf/x86: Add compiler barrier after updating BTS

[tip-bot2 for Leo Yan]

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     41100833cdd8b1bef363b81a6482d74711c116ad
Gitweb:        https://git.kernel.org/tip/41100833cdd8b1bef363b81a6482d74711c116ad
Author:        Leo Yan <leo.yan@xxxxxxxxxx>
AuthorDate:    Mon, 09 Aug 2021 19:14:02 +08:00
Committer:     Peter Zijlstra <peterz@xxxxxxxxxxxxx>
CommitterDate: Fri, 17 Sep 2021 15:08:38 +02:00

perf/x86: Add compiler barrier after updating BTS

Since BTS is coherent, simply add a compiler barrier to separate the BTS
update and aux_head store.

Signed-off-by: Leo Yan <leo.yan@xxxxxxxxxx>
Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
Link: https://lkml.kernel.org/r/20210809111407.596077-5-leo.yan@xxxxxxxxxx
---
 arch/x86/events/intel/bts.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c
index 6320d2c..974e917 100644
--- a/arch/x86/events/intel/bts.c
+++ b/arch/x86/events/intel/bts.c
@@ -209,6 +209,12 @@ static void bts_update(struct bts_ctx *bts)
 	} else {
 		local_set(&buf->data_size, head);
 	}
+
+	/*
+	 * Since BTS is coherent, just add compiler barrier to ensure
+	 * BTS updating is ordered against bts::handle::event.
+	 */
+	barrier();
 }
 
 static int