Re: [PATCH v2 5/5] clk: samsung: Introduce Exynos850 clock driver

[Sam Protsenko]

On Fri, 8 Oct 2021 at 09:54, Krzysztof Kozlowski
<krzysztof.kozlowski@xxxxxxxxxxxxx> wrote:
>
> On 07/10/2021 21:41, Sam Protsenko wrote:
> > This is the initial implementation adding only basic clocks like UART,
> > MMC, I2C and corresponding parent clocks. Design is influenced by
> > Exynos5433 clock driver.
> >
> > Bus clock is enabled by default (in probe function) for all CMUs except
> > CMU_TOP, the reasoning is as follows. By default if bus clock has no
> > users its "enable count" value is 0. It might be actually running if
> > it's already enabled in bootloader, but then in some cases it can be
> > disabled by mistake. For example, such case was observed when
> > dw_mci_probe() enabled the bus clock, then failed to do something and
> > disabled that bus clock on error path. After that, even the attempt to
> > read the 'clk_summary' file in DebugFS freezed forever, as CMU bus clock
> > ended up being disabled and it wasn't possible to access CMU registers
> > anymore.
> >
> > To avoid such cases, CMU driver must increment the ref count for that
> > bus clock by running clk_prepare_enable(). There is already existing
> > '.clk_name' field in struct samsung_cmu_info, exactly for that reason.
> > It was added in commit 523d3de41f02 ("clk: samsung: exynos5433: Add
> > support for runtime PM"), with next mentioning in commit message:
> >
> >   > Also for each CMU there is one special parent clock, which has to be
> >   > enabled all the time when any access to CMU registers is being done.
> >
> > But that clock is actually only enabled in Exynos5433 clock driver right
> > now. So the same code is added to exynos850_cmu_probe() function,
> > As was described above, it might be helpful not only for PM reasons, but
> > also to prevent possible erroneous clock gating on error paths.
> >
> > Another way to workaround that issue would be to use CLOCK_IS_CRITICAL
> > flag for corresponding gate clocks. But that might be not very good
> > design decision, as we might still want to disable that bus clock, e.g.
> > on PM suspend.
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> > ---
> > Changes in v2:
> >   - Used of_iomap() for the whole CMU range instead of ioremap() in
> >     exynos850_init_clocks()
> >   - Used readl/writel functions in exynos850_init_clocks() for consistency
> >     with other drivers
> >   - Added all clock ids
> >   - Added CMU_DPU
> >   - Implemented platform_driver for all Power Domain capable CMUs
> >   - Moved bus clock enablement code here to probe function
> >   - Used clk_get() instead of __clk_lookup()
> >
> >  drivers/clk/samsung/Makefile        |   1 +
> >  drivers/clk/samsung/clk-exynos850.c | 835 ++++++++++++++++++++++++++++
> >  2 files changed, 836 insertions(+)
> >  create mode 100644 drivers/clk/samsung/clk-exynos850.c
> >
>
> Thanks for the changes, awesome work, I appreciate it.
>

Thank you for review, Krzysztof! I'll send v3 soon. Hope this series
can be applied before next merge window.

> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxxxxx>
>
> Best regards,
> Krzysztof