RE: [PATCH v2 00/15] PHY: Add support for multilink configurations in Cadence Sierra PHY driver

[Swapnil Kashinath Jakhade]

Hi Vinod,

> -----Original Message-----
> From: Aswath Govindraju <a-govindraju@xxxxxx>
> Sent: Wednesday, September 15, 2021 8:44 PM
> To: Swapnil Kashinath Jakhade <sjakhade@xxxxxxxxxxx>;
> vkoul@xxxxxxxxxx; kishon@xxxxxx; robh+dt@xxxxxxxxxx;
> p.zabel@xxxxxxxxxxxxxx; linux-phy@xxxxxxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx
> Cc: Milind Parab <mparab@xxxxxxxxxxx>; lokeshvutla@xxxxxx
> Subject: Re: [PATCH v2 00/15] PHY: Add support for multilink configurations
> in Cadence Sierra PHY driver
> 
> EXTERNAL MAIL
> 
> 
> 
> On 08/09/21 5:59 pm, Swapnil Jakhade wrote:
> > Cadence Sierra PHY is a multiprotocol PHY supporting different
> > multilink PHY configurations. This patch series extends functionality
> > of Sierra PHY driver by adding features like support for multilink
> > multiprotocol configurations, derived reference clock etc.
> >
> > The changes have been validated on TI J721E platform.
> >
> > Version History:
> >
> > v2:
> >    - Added a new patch 3/15 to rename the SSC macros for dt-bindings
> >      to use generic names. These macros are not yet used in any DTS file.
> >
> > Swapnil Jakhade (15):
> >   phy: cadence: Sierra: Use of_device_get_match_data() to get driver
> >     data
> >   phy: cadence: Sierra: Prepare driver to add support for multilink
> >     configurations
> >   dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic
> >     names
> >   dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
> >   phy: cadence: Sierra: Add support to get SSC type from device tree
> >   phy: cadence: Sierra: Rename some regmap variables to be in sync with
> >     Sierra documentation
> >   phy: cadence: Sierra: Add PHY PCS common register configurations
> >   phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
> >   phy: cadence: Sierra: Check PIPE mode PHY status to be ready for
> >     operation
> >   phy: cadence: Sierra: Update single link PCIe register configuration
> >   phy: cadence: Sierra: Fix to get correct parent for mux clocks
> >   phy: cadence: Sierra: Add support for PHY multilink configurations
> >   phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
> >   dt-bindings: phy: cadence-sierra: Add clock ID for derived reference
> >     clock
> >   phy: cadence: Sierra: Add support for derived reference clock output
> >
> 
> for the complete series,
> 
> Reviewed-by: Aswath Govindraju <a-govindraju@xxxxxx>
> 
> Thanks,
> Aswath
> 

Could you please consider merging this series if looks okay.

Thanks & regards,
Swapnil

> >  .../bindings/phy/phy-cadence-sierra.yaml      |    9 +
> >  .../bindings/phy/phy-cadence-torrent.yaml     |    4 +-
> >  drivers/phy/cadence/phy-cadence-sierra.c      | 1299 +++++++++++++++--
> >  include/dt-bindings/phy/phy-cadence.h         |    9 +-
> >  4 files changed, 1226 insertions(+), 95 deletions(-)
> >