[PATCH] arm64: dts: mediatek: mt8173: remove double 'assigned-clocks' binding

[Dafna Hirschfeld]

The clock '<&topckgen CLK_TOP_VENC_LT_SEL>' is declared twice
in an 'assigned-clocks' list - in vcodec_dec and in
vcodec_enc_vp8. Fix it to be declared only in vcodec_enc_vp8

Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@xxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index d9e005ae5bb0..51781444cedd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1422,15 +1422,13 @@
 				      "vencpll",
 				      "venc_lt_sel",
 				      "vdec_bus_clk_src";
-			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
-					  <&topckgen CLK_TOP_CCI400_SEL>,
+			assigned-clocks = <&topckgen CLK_TOP_CCI400_SEL>,
 					  <&topckgen CLK_TOP_VDEC_SEL>,
 					  <&apmixedsys CLK_APMIXED_VCODECPLL>,
 					  <&apmixedsys CLK_APMIXED_VENCPLL>;
-			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
-						 <&topckgen CLK_TOP_UNIVPLL_D2>,
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D2>,
 						 <&topckgen CLK_TOP_VCODECPLL>;
-			assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
+			assigned-clock-rates = <0>, <0>, <1482000000>, <800000000>;
 		};
 
 		larb1: larb@16010000 {
-- 
2.17.1