Add some basic documentation (zh_CN version) for LoongArch. LoongArch is
a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a
reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a
64-bit version (LA64).
Reviewed-by: Alex Shi <alexs@xxxxxxxxxx>
Reviewed-by: Yanteng Si <siyanteng@xxxxxxxxxxx>
Signed-off-by: Huacai Chen <chenhuacai@xxxxxxxxxxx>
---
Documentation/translations/zh_CN/index.rst | 1 +
.../translations/zh_CN/loongarch/features.rst | 8 +
.../translations/zh_CN/loongarch/index.rst | 26 ++
.../zh_CN/loongarch/introduction.rst | 351 ++++++++++++++++++
.../zh_CN/loongarch/irq-chip-model.rst | 167 +++++++++
5 files changed, 553 insertions(+)
create mode 100644 Documentation/translations/zh_CN/loongarch/features.rst
create mode 100644 Documentation/translations/zh_CN/loongarch/index.rst
create mode 100644 Documentation/translations/zh_CN/loongarch/introduction.rst
create mode 100644 Documentation/translations/zh_CN/loongarch/irq-chip-model.rst