Hi Michal,
Thank you for the patch.
On Tue, May 02, 2023 at 03:35:29PM +0200, Michal Simek wrote:
TI DP83867 is using strapping based on MIO pins. Tristate setup can influce
PHY address. That's why switch description with ethernet-phy-id compatible
string which enable calling reset. PHY itself setups phy address after
power up or reset.
I'm sorry but I don't understand this :-(
Phy reset is done via gpio.
Signed-off-by: Michal Simek <michal.simek@xxxxxxx>
---
Checkpatch is reporting issue
warning: DT compatible string "ethernet-phy-id2000.a231" appears un-documented
but it should be fully aligned with
Documentation/devicetree/bindings/net/ethernet-phy.yaml
---
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 23 +++++++++++------
.../boot/dts/xilinx/zynqmp-zcu102-revB.dts | 25 +++++++++++--------
.../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 22 ++++++++++------
.../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 22 ++++++++++------
.../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 22 ++++++++++------
.../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 22 ++++++++++------
6 files changed, 90 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index 13c43324f1d2..c193579400cf 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -2,7 +2,8 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
- * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ * (C) Copyright 2015 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@xxxxxxxxxx>
*/
@@ -200,13 +201,19 @@ &gem3 {
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
- phy0: ethernet-phy@21 {
- reg = <21>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
- /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+ mdio: mdio {
The "mdio" label isn't needed. Same below.