Re: [PATCH 0/2] perf: add T-HEAD C9xx series cpu support

[Nikita Shubin]

Hello Inochi Amaoto!

Thank you for your series!

Could you also provide HPM device tree bindings which were used in
OpenSBI for testing in cover letter ?

On Tue, 2023-05-16 at 10:37 +0800, Inochi Amaoto wrote:
> The T-HEAD C9xx series cpu is a series of riscv CPU IP. As this IP
> was
> proposed before the current riscv event standard. It has a non-
> standard
> events encoding for perf events and unimplemented MARCH and MIMP CSR.
> This patch add these events to support C9xx cpus.
> 
> AFAIK, at least the following chips used C9xx cpu.
> 
> * Allwinner D1 (C906)
> * T-HEAD th1520 (C910)
> * Sophgo mango (C920)
> 
> Inochi Amaoto (2):
>   perf tools riscv: Allow get_cpuid return empty MARCH and MIMP
>   perf vendor events riscv: add T-HEAD C9xx JSON file
> 
>  tools/perf/arch/riscv/util/header.c           |  7 +-
>  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
>  .../arch/riscv/t-head/c9xx/cache.json         | 67
> ++++++++++++++++++
>  .../arch/riscv/t-head/c9xx/firmware.json      | 68
> +++++++++++++++++++
>  .../arch/riscv/t-head/c9xx/instruction.json   | 22 ++++++
>  .../arch/riscv/t-head/c9xx/microarch.json     | 42 ++++++++++++
>  6 files changed, 201 insertions(+), 6 deletions(-)
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/cache.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json
> 
> --
> 2.40.1
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@xxxxxxxxxxxxxxxxxxx
> http://lists.infradead.org/mailman/listinfo/linux-riscv