[PATCH 3/3] dmaengine: ae4dma: Add debugfs entries for AE4DMA

From: Sanjay R Mehta
Date: Mon Sep 11 2023 - 16:50:30 EST

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In reply to: Sanjay R Mehta: "[PATCH 0/3] Add support for AMD AE4DMA controller driver"
Next in thread: Sanjay R Mehta: "[PATCH 2/3] dmaengine: ae4dma: register AE4DMA controller as a DMA resource"
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From: Sanjay R Mehta <sanju.mehta@xxxxxxx>

Expose data about the configuration and operation of the
AE4DMA through debugfs entries: device name, capabilities,
configuration, statistics.

Signed-off-by: Sanjay R Mehta <sanju.mehta@xxxxxxx>
---
drivers/dma/ae4dma/Makefile | 2 +-
drivers/dma/ae4dma/ae4dma-debugfs.c | 98 +++++++++++++++++++++++++++++++++++++
drivers/dma/ae4dma/ae4dma-dev.c | 16 ++++++
drivers/dma/ae4dma/ae4dma.h | 8 +++
4 files changed, 123 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/ae4dma/ae4dma-debugfs.c

diff --git a/drivers/dma/ae4dma/Makefile b/drivers/dma/ae4dma/Makefile
index b1e4318..4082fec 100644
--- a/drivers/dma/ae4dma/Makefile
+++ b/drivers/dma/ae4dma/Makefile
@@ -5,6 +5,6 @@

obj-$(CONFIG_AMD_AE4DMA) += ae4dma.o

-ae4dma-objs := ae4dma-dev.o ae4dma-dmaengine.o
+ae4dma-objs := ae4dma-dev.o ae4dma-dmaengine.o ae4dma-debugfs.o

ae4dma-$(CONFIG_PCI) += ae4dma-pci.o
diff --git a/drivers/dma/ae4dma/ae4dma-debugfs.c b/drivers/dma/ae4dma/ae4dma-debugfs.c
new file mode 100644
index 0000000..ae6ec7d
--- /dev/null
+++ b/drivers/dma/ae4dma/ae4dma-debugfs.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * AMD AE4DMA device driver
+ * -- Based on the PTDMA driver
+ *
+ * Copyright (C) 2023 Advanced Micro Devices, Inc.
+ *
+ * Author: Sanjay R Mehta <sanju.mehta@xxxxxxx>
+ */
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+#include "ae4dma.h"
+
+/* DebugFS helpers */
+#define RI_VERSION_NUM 0x0000003F
+
+#define RI_NUM_VQM 0x00078000
+#define RI_NVQM_SHIFT 15
+
+static int ae4_debugfs_info_show(struct seq_file *s, void *p)
+{
+ struct ae4_device *ae4 = s->private;
+ unsigned int regval;
+
+ seq_printf(s, "Device name: %s\n", dev_name(ae4->dev));
+ seq_printf(s, " # Queues: %d\n", 1);
+ seq_printf(s, " # Cmds: %d\n", ae4->cmd_count);
+
+ regval = ioread32(ae4->io_regs + CMD_AE4_VERSION);
+
+ seq_printf(s, " Version: %d\n", regval & RI_VERSION_NUM);
+ seq_puts(s, " Engines:");
+ seq_puts(s, "\n");
+ seq_printf(s, " Queues: %d\n", (regval & RI_NUM_VQM) >> RI_NVQM_SHIFT);
+
+ return 0;
+}
+
+/*
+ * Return a formatted buffer containing the current
+ * statistics of queue for AE4DMA
+ */
+static int ae4_debugfs_stats_show(struct seq_file *s, void *p)
+{
+ struct ae4_device *ae4 = s->private;
+
+ seq_printf(s, "Total Interrupts Handled: %ld\n", ae4->total_interrupts);
+
+ return 0;
+}
+
+static int ae4_debugfs_queue_show(struct seq_file *s, void *p)
+{
+ struct ae4_cmd_queue *cmd_q = s->private;
+
+ if (!cmd_q)
+ return 0;
+
+ seq_printf(s, " Total CMDs submitted: %ld\n", cmd_q->total_ae4_ops);
+ seq_printf(s, " Total CMDs in q%d: %ld\n", cmd_q->id, cmd_q->q_cmd_count);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(ae4_debugfs_info);
+DEFINE_SHOW_ATTRIBUTE(ae4_debugfs_queue);
+DEFINE_SHOW_ATTRIBUTE(ae4_debugfs_stats);
+
+void ae4dma_debugfs_setup(struct ae4_device *ae4)
+{
+ struct ae4_cmd_queue *cmd_q;
+ struct dentry *debugfs_q_instance;
+ unsigned int i;
+ char name[30];
+
+ if (!debugfs_initialized())
+ return;
+
+ debugfs_create_file("info", 0400, ae4->dma_dev.dbg_dev_root, ae4,
+ &ae4_debugfs_info_fops);
+
+ debugfs_create_file("stats", 0400, ae4->dma_dev.dbg_dev_root, ae4,
+ &ae4_debugfs_stats_fops);
+
+ for (i = 0; i < ae4->cmd_q_count; i++) {
+ cmd_q = &ae4->cmd_q[i];
+
+ snprintf(name, 29, "q%d", cmd_q->id);
+
+ debugfs_q_instance =
+ debugfs_create_dir(name, ae4->dma_dev.dbg_dev_root);
+
+ debugfs_create_file("stats", 0400, debugfs_q_instance, cmd_q,
+ &ae4_debugfs_queue_fops);
+ }
+}
diff --git a/drivers/dma/ae4dma/ae4dma-dev.c b/drivers/dma/ae4dma/ae4dma-dev.c
index af7e510..fe5af0c0 100644
--- a/drivers/dma/ae4dma/ae4dma-dev.c
+++ b/drivers/dma/ae4dma/ae4dma-dev.c
@@ -74,6 +74,7 @@ static int ae4_core_execute_cmd(struct ae4dma_desc *desc, struct ae4_cmd_queue *
{
bool soc = FIELD_GET(DWORD0_SOC, desc->dw0);
u8 *q_desc = (u8 *)&cmd_q->qbase[0];
+ unsigned long flags;
u32 tail_wi;

cmd_q->int_rcvd = 0;
@@ -99,6 +100,10 @@ static int ae4_core_execute_cmd(struct ae4dma_desc *desc, struct ae4_cmd_queue *
tail_wi = (tail_wi + 1) % CMD_Q_LEN;
iowrite32(tail_wi, cmd_q->reg_control + 0x10);

+ spin_lock_irqsave(&cmd_q->cmd_lock, flags);
+ cmd_q->q_cmd_count++;
+ spin_unlock_irqrestore(&cmd_q->cmd_lock, flags);
+
mutex_unlock(&cmd_q->q_mutex);

return 0;
@@ -110,6 +115,7 @@ int ae4_core_perform_passthru(struct ae4_cmd_queue *cmd_q, struct ae4_passthru_e
struct ae4_device *ae4 = cmd_q->ae4;

cmd_q->cmd_error = 0;
+ cmd_q->total_ae4_ops++;
memset(&desc, 0, sizeof(desc));
desc.dw0 = CMD_DESC_DW0_VAL;
desc.dw1.status = 0;
@@ -173,9 +179,12 @@ static irqreturn_t ae4_core_irq_handler(int irq, void *data)
{
struct ae4_cmd_queue *cmd_q = data;
struct ae4_device *ae4 = cmd_q->ae4;
+ unsigned long flags;
u32 status = ioread32(cmd_q->reg_control + 0x4);
u8 q_intr_type = (status >> 24) & 0xf;

+ ae4->total_interrupts++;
+
if (q_intr_type == 0x4)
dev_info(ae4->dev, "AE4DMA INTR: %s (0x%x)\n", "queue desc error", q_intr_type);
else if (q_intr_type == 0x2)
@@ -187,6 +196,10 @@ static irqreturn_t ae4_core_irq_handler(int irq, void *data)

ae4_check_status_trans(ae4, cmd_q);

+ spin_lock_irqsave(&cmd_q->cmd_lock, flags);
+ cmd_q->q_cmd_count--;
+ spin_unlock_irqrestore(&cmd_q->cmd_lock, flags);
+
tasklet_schedule(&cmd_q->irq_tasklet);

return IRQ_HANDLED;
@@ -283,6 +296,9 @@ int ae4_core_init(struct ae4_device *ae4)
if (ret)
goto e_free_irq;

+ /* Set up debugfs entries */
+ ae4dma_debugfs_setup(ae4);
+
return 0;

e_free_irq:
diff --git a/drivers/dma/ae4dma/ae4dma.h b/drivers/dma/ae4dma/ae4dma.h
index d341c35..ae31b26 100644
--- a/drivers/dma/ae4dma/ae4dma.h
+++ b/drivers/dma/ae4dma/ae4dma.h
@@ -231,6 +231,10 @@ struct ae4_cmd_queue {
wait_queue_head_t q_space;
unsigned int q_space_available;

+ /* Queue Statistics */
+ unsigned long total_ae4_ops;
+ unsigned long q_cmd_count;
+
struct ae4_tasklet_data tdata;
struct tasklet_struct irq_tasklet;

@@ -274,6 +278,9 @@ struct ae4_device {
struct kmem_cache *dma_desc_cache;

wait_queue_head_t lsb_queue;
+
+ /* Device Statistics */
+ unsigned long total_interrupts;
};

/*
@@ -326,6 +333,7 @@ struct ae4_dev_vdata {
int ae4_dmaengine_register(struct ae4_device *ae4);
void ae4_dmaengine_unregister(struct ae4_device *ae4);

+void ae4dma_debugfs_setup(struct ae4_device *ae4);
int ae4_core_init(struct ae4_device *ae4);
void ae4_core_destroy(struct ae4_device *ae4);

--
2.7.4

Next message: Maximilian Heyne: "[PATCH v3] virtio-mmio: fix memory leak of vm_dev"
Previous message: Rob Herring: "Re: [PATCH v3 10/13] dt-bindings: power: Clarify performance capabilities of power-domains"
In reply to: Sanjay R Mehta: "[PATCH 0/3] Add support for AMD AE4DMA controller driver"
Next in thread: Sanjay R Mehta: "[PATCH 2/3] dmaengine: ae4dma: register AE4DMA controller as a DMA resource"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]