Re: [PATCH v4 0/4] rockchip: add GATE_LINK
From: zhangqing
Date: Wed Oct 25 2023 - 22:33:49 EST
在 2023/10/26 5:40, Stephen Boyd 写道:
Quoting Sebastian Reichel (2023-10-25 12:48:49)
Hello Stephen,
On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote:
Quoting Elaine Zhang (2023-10-18 00:01:40)
Recent Rockchip SoCs have a new hardware block called Native Interface
Unit (NIU), which gates clocks to devices behind them. These effectively
need two parent clocks.
Use GATE_LINK to handle this.
Why can't pm clks be used here? The qcom clk driver has been doing that
for some time now.
$ git grep pm_clk_add -- drivers/clk/qcom/
Maybe I'm mistaken, but as far as I can tell this is adding the
dependency on controller level and only works because Qualcomm
has multiple separate clock controllers. In the Rockchip design
there is only one platform device.
Note, that the original downstream code from Rockchip actually used
pm_clk infrastructure by moving these clocks to separate platform
devices. I changed this when upstreaming the code, since that leaks
into DT and from DT point of view there should be only one clock
controller.
Why can't the rockchip driver bind to a single device node and make
sub-devices for each clk domain and register clks for those? Maybe it
can use the auxiliary driver infrastructure to do that?
Option 1:
Use the current patch to adapt the GATE_LINK type upstream.
The real function of GATE_LINK is implemented。
Just to improve and adapt the existing features on upstream.
Option 2:
What we use on our internal branches are:
drivers/clk/rockchip/clk-link.c
static int rockchip_clk_link_probe(struct platform_device *pdev)
{
struct rockchip_link_clk *priv;
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *match;
const char *clk_name;
const struct rockchip_link_info *link_info;
int ret;
match = of_match_node(rockchip_clk_link_of_match, node);
if (!match)
return -ENXIO;
priv = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_link_clk),
GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->link = match->data;
spin_lock_init(&priv->lock);
platform_set_drvdata(pdev, priv);
priv->base = of_iomap(node, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
if (of_property_read_string(node, "clock-output-names", &clk_name))
priv->name = node->name;
else
priv->name = clk_name;
link_info = rockchip_get_link_infos(priv->link, priv->name);
priv->shift = link_info->shift;
priv->pname = link_info->pname;
pm_runtime_enable(&pdev->dev);
ret = pm_clk_create(&pdev->dev);
if (ret)
goto disable_pm_runtime;
ret = pm_clk_add(&pdev->dev, "link");
if (ret)
goto destroy_pm_clk;
ret = register_clocks(priv, &pdev->dev);
if (ret)
goto destroy_pm_clk;
return 0;
destroy_pm_clk:
pm_clk_destroy(&pdev->dev);
disable_pm_runtime:
pm_runtime_disable(&pdev->dev);
return ret;
}
Both of these methods are OK. Whichever one Upstream prefers, I can
submit it as required.
--
张晴
瑞芯微电子股份有限公司
Rockchip Electronics Co.,Ltd
地址：福建省福州市铜盘路软件大道89号软件园A区21号楼
Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China
Tel:+86-0591-83991906-8601
邮编：350003
E-mail:elaine.zhang@xxxxxxxxxxxxxx
****************************************************************************
保密提示：本邮件及其附件含有机密信息，仅发送给本邮件所指特定收件人。若非该特定收件人，请勿复制、使用或披露本邮件的任何内容。若误收本邮件，请从系统中永久性删除本邮件及所有附件，并以回复邮件或其他方式即刻告知发件人。福州瑞芯微电子有限公司拥有本邮件信息的著作权及解释权，禁止任何未经授权许可的侵权行为。
IMPORTANT NOTICE: This email is from Fuzhou Rockchip Electronics Co., Ltd .The contents of this email and any attachments may contain information that is privileged, confidential and/or exempt from disclosure under applicable law and relevant NDA. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information is STRICTLY PROHIBITED. Please immediately contact the sender as soon as possible and destroy the material in its entirety in any format. Thank you.
****************************************************************************