Re: [PATCH v4 06/17] drm/mediatek: Support alpha blending in OVL

From: CK Hu (胡俊光)
Date: Tue Jan 02 2024 - 00:43:56 EST

Next message: Zhipeng Lu: "[PATCH] [v3] SUNRPC: fix some memleaks in gssx_dec_option_array"
Previous message: Stephen Rothwell: "linux-next: build warning after merge of the mm tree"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Hi, Hsiao-chien:

On Tue, 2023-12-12 at 20:19 +0800, Hsiao Chien Sung wrote:
> Support premultiply and coverage alpha blending in
> Overlay.

Describe what kind of alpha blending already support for cursor plane.
And separate premultiply alpha and coverage alpha to two patches.

>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 73 +++++++++++++++++----
> ----
> 1 file changed, 51 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 5aaf4342cdbd..66074c2d917c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -39,6 +39,7 @@
> #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n))
> #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16)
> #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20
> * (n))
> +#define OVL_CONST_BLEND BIT(28)
> #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
> #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
> #define DISP_REG_OVL_ADDR_MT2701 0x0040
> @@ -52,13 +53,16 @@
> #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
> #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
>
> -#define OVL_CON_BYTE_SWAP BIT(24)
> -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
> -#define OVL_CON_CLRFMT_RGB (1 << 12)
> -#define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
> -#define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
> -#define OVL_CON_CLRFMT_UYVY (4 << 12)
> -#define OVL_CON_CLRFMT_YUYV (5 << 12)
> +#define OVL_CON_CLRFMT_MAN BIT(23)
> +#define OVL_CON_BYTE_SWAP BIT(24)
> +#define OVL_CON_RGB_SWAP BIT(25)
> +#define OVL_CON_CLRFMT_RGB (1 << 12)
> +#define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
> +#define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
> +#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 |
> OVL_CON_CLRFMT_MAN)
> +#define OVL_CON_CLRFMT_UYVY (4 << 12)
> +#define OVL_CON_CLRFMT_YUYV (5 << 12)
> +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
> #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ?
> \
> 0 : OVL_CON_CLRFMT_RGB)
> #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ?
> \
> @@ -208,14 +212,12 @@ void mtk_ovl_clk_disable(struct device *dev)
> void mtk_ovl_start(struct device *dev)
> {
> struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
> + unsigned int reg = readl(ovl->regs +
> DISP_REG_OVL_DATAPATH_CON);
>
> - if (ovl->data->smi_id_en) {
> - unsigned int reg;
> + if (ovl->data->smi_id_en)
> + reg |= OVL_LAYER_SMI_ID_EN;
>
> - reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
> - reg = reg | OVL_LAYER_SMI_ID_EN;
> - writel_relaxed(reg, ovl->regs +
> DISP_REG_OVL_DATAPATH_CON);
> - }
> + writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);

Nothing change in this function, so drop this modification.

> writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
> }
>
> @@ -274,7 +276,13 @@ void mtk_ovl_config(struct device *dev, unsigned
> int w,
> if (w != 0 && h != 0)
> mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl-
> >cmdq_reg, ovl->regs,
> DISP_REG_OVL_ROI_SIZE);
> - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_ROI_BGCLR);
> +
> + /*
> + * The background color should be opaque black (ARGB),
> + * otherwise there will be no effect with alpha blend
> + */
> + mtk_ddp_write_relaxed(cmdq_pkt, 0xff000000, &ovl->cmdq_reg,
> + ovl->regs, DISP_REG_OVL_ROI_BGCLR);

If cursor plane also has this problem, separate this to a bug-fix
patch. If only new alpha blending mode has this problem, describe more
detail why new blending mode has this problem.

Regards,
CK

>
> mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_RST);
> mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_RST);
> @@ -357,7 +365,8 @@ void mtk_ovl_layer_off(struct device *dev,
> unsigned int idx,
> DISP_REG_OVL_RDMA_CTRL(idx));
> }
>
> -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl,
> unsigned int fmt)
> +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl,
> unsigned int fmt,
> + unsigned int blend_mode)
> {
> /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
> * is defined in mediatek HW data sheet.
> @@ -376,18 +385,30 @@ static unsigned int ovl_fmt_convert(struct
> mtk_disp_ovl *ovl, unsigned int fmt)
> return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_RGBX8888:
> case DRM_FORMAT_RGBA8888:
> - return OVL_CON_CLRFMT_ARGB8888;
> + return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> + OVL_CON_CLRFMT_ARGB8888 :
> + OVL_CON_CLRFMT_PARGB8888;
> case DRM_FORMAT_BGRX8888:
> case DRM_FORMAT_BGRA8888:
> + return OVL_CON_BYTE_SWAP |
> + (blend_mode == DRM_MODE_BLEND_COVERAGE ?
> + OVL_CON_CLRFMT_ARGB8888 :
> + OVL_CON_CLRFMT_PARGB8888);
> case DRM_FORMAT_BGRA1010102:
> return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
> case DRM_FORMAT_XRGB8888:
> case DRM_FORMAT_ARGB8888:
> + return blend_mode == DRM_MODE_BLEND_COVERAGE ?
> + OVL_CON_CLRFMT_RGBA8888 :
> + OVL_CON_CLRFMT_PARGB8888;
> case DRM_FORMAT_ARGB2101010:
> return OVL_CON_CLRFMT_RGBA8888;
> case DRM_FORMAT_XBGR8888:
> case DRM_FORMAT_ABGR8888:
> - return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
> + return OVL_CON_RGB_SWAP |
> + (blend_mode == DRM_MODE_BLEND_COVERAGE ?
> + OVL_CON_CLRFMT_RGBA8888 :
> + OVL_CON_CLRFMT_PARGB8888);
> case DRM_FORMAT_UYVY:
> return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
> case DRM_FORMAT_YUYV:
> @@ -408,6 +429,8 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
> unsigned int fmt = pending->format;
> unsigned int offset = (pending->y << 16) | pending->x;
> unsigned int src_size = (pending->height << 16) | pending-
> >width;
> + unsigned int blend_mode = state->base.pixel_blend_mode;
> + unsigned int ignore_pixel_alpha = 0;
> unsigned int con;
> bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
> union overlay_pitch {
> @@ -425,9 +448,15 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
> return;
> }
>
> - con = ovl_fmt_convert(ovl, fmt);
> - if (state->base.fb && state->base.fb->format->has_alpha)
> - con |= OVL_CON_AEN | OVL_CON_ALPHA;
> + con = ovl_fmt_convert(ovl, fmt, blend_mode);
> + if (state->base.fb) {
> + con |= OVL_CON_AEN;
> + con |= state->base.alpha & OVL_CON_ALPHA;
> + }
> +
> + if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> + (state->base.fb && !state->base.fb->format->has_alpha))
> + ignore_pixel_alpha = OVL_CONST_BLEND;
>
> if (pending->rotation & DRM_MODE_REFLECT_Y) {
> con |= OVL_CON_VIRT_FLIP;
> @@ -444,8 +473,8 @@ void mtk_ovl_layer_config(struct device *dev,
> unsigned int idx,
>
> mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_CON(idx));
> - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb,
> &ovl->cmdq_reg, ovl->regs,
> - DISP_REG_OVL_PITCH(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb |
> ignore_pixel_alpha,
> + &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_PITCH(idx));
> mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl-
> >regs,
> DISP_REG_OVL_SRC_SIZE(idx));
> mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl-
> >regs,

Next message: Zhipeng Lu: "[PATCH] [v3] SUNRPC: fix some memleaks in gssx_dec_option_array"
Previous message: Stephen Rothwell: "linux-next: build warning after merge of the mm tree"
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]