On Sun, Jan 21, 2024 at 08:42:36PM +0800, Ziyang Huang wrote:
Signed-off-by: Ziyang Huang <hzyitc@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 120 +++++++++++++++++++++++++-
1 file changed, 116 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index e502a3ecf4b7..b36e5c2136b7 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -94,6 +94,63 @@ soc: soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ mdio0: mdio@88000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio";
+ reg = <0x88000 0x64>;
+ resets = <&gcc GCC_GEPHY_MDC_SW_ARES>,
+ <&gcc GCC_GEPHY_DSP_HW_ARES>;
What do these two resets do? An MDIO bus controller is unlikely to
have a DSP in it. That is something a PHY is more likely to have. An
MDIO bus controller does have an MDC line, but why is it
GCC_GEPHY_MDC_SW_ARES not GCC_MDIO_MDC_SW_ARES? So this again makes me
think this is a PHY reset, so should be in the PHY node.
A device tree binding will help sort this out.
Andrew
---
pw-bot: cr