[PATCH RFC 1/2] dt-bindings: soc: qcom,smsm: Allow specifying mboxes instead of qcom,ipc

From: Luca Weiss
Date: Wed Apr 24 2024 - 13:22:20 EST


The qcom,ipc-N properties are essentially providing a reference to a
mailbox, so allow using the mboxes property to do the same in a more
structured way.

Since multiple SMSM hosts are supported, we need to be able to provide
the correct mailbox for each host. The old qcom,ipc-N properties map to
the mboxes property by index, starting at 0 since that's a valid SMSM
host also.

The new example shows how an smsm node with just qcom,ipc-3 should be
specified with the mboxes property.

Signed-off-by: Luca Weiss <luca@xxxxxxxxx>
---
.../devicetree/bindings/soc/qcom/qcom,smsm.yaml | 48 ++++++++++++++++++----
1 file changed, 40 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml
index db67cf043256..b12589171169 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml
@@ -33,6 +33,13 @@ properties:
specifier of the column in the subscription matrix representing the local
processor.

+ mboxes:
+ minItems: 1
+ maxItems: 5
+ description:
+ Reference to the mailbox representing the outgoing doorbell in APCS for
+ this client.
+
'#size-cells':
const: 0

@@ -98,15 +105,18 @@ required:
- '#address-cells'
- '#size-cells'

-anyOf:
+oneOf:
- required:
- - qcom,ipc-1
- - required:
- - qcom,ipc-2
- - required:
- - qcom,ipc-3
- - required:
- - qcom,ipc-4
+ - mboxes
+ - anyOf:
+ - required:
+ - qcom,ipc-1
+ - required:
+ - qcom,ipc-2
+ - required:
+ - qcom,ipc-3
+ - required:
+ - qcom,ipc-4

additionalProperties: false

@@ -136,3 +146,25 @@ examples:
#interrupt-cells = <2>;
};
};
+ # Example using mboxes property
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ shared-memory {
+ compatible = "qcom,smsm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mboxes = <0>, <0>, <0>, <&apcs 19>;
+
+ apps@0 {
+ reg = <0>;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcnss@7 {
+ reg = <7>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };

--
2.44.0