Re: [PATCH net-next v2 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for MT7530

From: Arınç ÜNAL
Date: Sat Apr 27 2024 - 07:40:56 EST


On 27.04.2024 05:24, Daniel Golle wrote:
Hi Arınç,

On Mon, Apr 22, 2024 at 10:15:14AM +0300, Arınç ÜNAL via B4 Relay wrote:
From: Arınç ÜNAL <arinc.unal@xxxxxxxxxx>

On MT7530, the media-independent interfaces of port 5 and 6 are controlled
by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
these bits only when the relevant port is being enabled or disabled. This
ensures that these ports will be disabled when they are not in use.

Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
done on mt7530_setup().

Multiple users reported ([1], [2]) that after I've imported the series
to OpenWrt they noticed that WAN connection on MT7621 boards using
PHY-muxing to hook up either port 0 or port 4 to GMAC1 no longer works.

The link still seems to come up, but no data flows. I went ahead and
confirmed the bug, then started bisecting the patches of this series,
and ended up identifying this very patch being the culprit.

I can't exclude that what ever the issue may be is caused by other
downstream patches we have, but can confirm that removing this patch of
your series [3] in OpenWrt fixes the issue. Please take a look and as
the cover letter states you have tested this on some MT7621 board,
please make sure traffic actually flows on the PHY-muxed port on that
board after this patch is applied, and if not, please figure out why and
repost a fixed version of this patch.


Cheers


Daniel

[1]: https://github.com/openwrt/openwrt/issues/15273
[2]: https://github.com/openwrt/openwrt/issues/15279
[3]: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commit;h=a8dde7e5bd6d289db6485cf57d3512ea62eaa827

Thanks for reporting this Daniel. I am not happy that I've caused all this
fuss. My testing as described on the cover letter did not include the
hardware design with PHY muxing. Lesson learned; next time, I'll make sure
to test the specific hardware design when I work on the part of the code
that would affect that hardware design.

That said, I've submitted a patch that fixes this issue [1]. I have tested
the hardware design with PHY muxing with this fix applied and I don't
experience this issue anymore.

[1] https://lore.kernel.org/netdev/20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@xxxxxxxxxx/

Arınç