Re: [PATCH V3 1/2] iommu/arm-smmu-v3: Add support for ECMDQ register mode

From: Leizhen (ThunderTown)
Date: Sat Apr 27 2024 - 22:19:43 EST




On 2024/4/25 22:41, Tanmay Jagdale wrote:
> +static int arm_smmu_ecmdq_probe(struct arm_smmu_device *smmu)
> +{
> + int ret, cpu;
> + u32 i, nump, numq, gap;
> + u32 reg, shift_increment;
> + u64 offset;
> + void __iomem *cp_regs, *cp_base;
> +
> + /* IDR6 */
> + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR6);
> + nump = 1 << FIELD_GET(IDR6_LOG2NUMP, reg);
> + numq = 1 << FIELD_GET(IDR6_LOG2NUMQ, reg);
> + smmu->nr_ecmdq = nump * numq;
> + gap = ECMDQ_CP_RRESET_SIZE >> FIELD_GET(IDR6_LOG2NUMQ, reg);
> +
> + cp_regs = ioremap(smmu->iobase + ARM_SMMU_ECMDQ_CP_BASE, PAGE_SIZE);
> + if (!cp_regs)
> + return -ENOMEM;
> +
> + for (i = 0; i < nump; i++) {
> + u64 val, pre_addr = 0;

This is my mistake. The 'pre_addr' should be defined out of this 'for' loop. Or, you
can remove all 'pre_addr' related statements, commercially available chips that have
been tested cannot have such errors.

> +
> + val = readq_relaxed(cp_regs + 32 * i);
> + if (!(val & ECMDQ_CP_PRESET)) {
> + iounmap(cp_regs);
> + dev_err(smmu->dev, "ecmdq control page %u is memory mode\n", i);
> + return -EFAULT;
> + }
> +

<---------------------------------------------
> + if (i && ((val & ECMDQ_CP_ADDR) != (pre_addr + ECMDQ_CP_RRESET_SIZE))) { |
> + iounmap(cp_regs); |
> + dev_err(smmu->dev, "ecmdq_cp memory region is not contiguous\n"); |
> + return -EFAULT; |
> + } |
> + |
> + pre_addr = val & ECMDQ_CP_ADDR; |
<-------------------------------------------- feel free remove these
> + }

--
Regards,
Zhen Lei