Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src

[Stephen Boyd]

Quoting Konrad Dybcio (2024-04-27 05:01:07)
> Similar to how it works on other SoCs, the top frequency of the SDHCI2
> core clock is generated by a separate PLL (peculiar design choice) that
> is not guaranteed to be enabled (why does the clock framework not handle
> this by default?).
> 
> Add the CLK_OPS_PARENT_ENABLE flag to make sure we're not muxing the
> RCG input to a dormant source.

The RCG2 hardware hasn't required the parent to be enabled for clk
operations besides for the glitch-free source switch. What scenario is
happening here that's requiring this flag? Is the RCG forcibly enabled
perhaps because the bootloader has left the root enable bit set
(CMD_ROOT_EN)? Or are we changing the parent while the clk framework
thinks the clk is off when it is actually on?

TL;DR: This is papering over a bigger bug.