There is an even worse problem with the buddy system, especially on CPU's
without 4 way caches. All our structures tend to have the used stuff at
the top and data below. Our kmalloc spends all day landing all the
critical structures on the same cache line..
> and the memory handle stuff isnt good for interrupt handlers ... neither
> for SMP? TLB invalidates are basically a hardware-implemented
> 'handle-invalidate' feature ... we cannot really implement this in
> software, can we?
Some CPU's the TLB is software. On all CPU's I know an SMP CPU invalidation
needs software and is relatively expensive.
Alan