Unfortunately, there is no BIOS function at this time that will report
the maximum address of cacheable memory. The warning would have to be
chipset-based (i.e. detect which chipset is on the board and display the
warning if it is appropriate); this is probably doable since there are not that
many chipsets floating around anyway.
> Would there still be systems out there which have this archiecture? I
> somehow doubt it, but watch out for the up coming NUMA machines. Each
> 'node' will have local memory, but will be able (at a cost) to access
> memory on other 'nodes' (a single address space).
That's a very good reason to implement a slow/fast page system, but I hope
that a NUMA system would not be limited by interrupt 15h to report its
actual memory distribution.
Cheers,
Kimon.
-- Kimon Berlin - Hewlett-Packard Performance Desktop Computing Operation R&D (BIOS), a spinoff of the Division Formerly Known as GPCD "You can tune a filesystem, but you can't tune a fish" [HP/UX tunefs(1M)]