> Something else that looks useful is the ability (only on the K5?) to
> not flush certain TLB entries on CR3 reloads. I believe that the Cyrix
> 6x86 also has a similar facility which actually locks some TLB enties
> in a special seperate table.
I can't remember seeing anything about locking TLBs. Maybe they were
talking about VSPM mappings (which have some, ah, "interesting"
problems anyway :-) ).
Talking of processor "features" I see that the Cyrix M2 has a way
of locking down an L1 cache line. Anyone care to speculate how that
could benefit us? Cyrix suggest that since L1 accesses are as fast
as register accesses you could use it to implement large register
files. We've all complained about how few general purpose registers
x86 chips have...
Mike
-- .----------------------------------------------------------------------. | Mike Jagdis | Internet: mailto:mike@roan.co.uk | | Roan Technology Ltd. | | | 54A Peach Street, Wokingham | Telephone: +44 118 989 0403 | | RG40 1XG, ENGLAND | Fax: +44 118 989 1195 | `----------------------------------------------------------------------'