>
> On Fri, 9 May 1997 16:11:57 +0200, you wrote:
>
> > I'm not absolutely sure as different specs contradict each other. For example,
> > Intel Triton PIIX datasheets clearly say these bits are always valid, on the other
> > hand Tech Help and several DOS port description guides define these bits as
> > XT keyboard disable. AMD-640 chipset specs don't mention this port at all
> > and OPTI Vendetta chipset specs state the same as Intel. => It seems bits 6 and 7
> > are always valid on modern MB's, but maybe not on the old ones.
> >
>
> Which means you can't have the kernel using these bits at all without knowing
> what hardware it's using. That's the problem. Any code that uses specific ports
> had better be absolutely sure it know what's going on.
>
> Also, I wouldn't depend on "modern" motherboards doing the same thing from one
> revision to another.
Hmmm ... is there a way to force an NMI (hardware, not just int 0x02) to
simulate a memory error, just to see if the relevant bits are set ?
> > Conclusion: We should not enable these bits explicitly and we should honor
> > the information in bits 6 and 7 only if the corresponding NMI sources are set
> > in bits 2 and 3 (they are hopefully readable on all MB's since the XT).
> >
> I don't think we should even read these bits because we don't *know* if they are
> valid. Only the use and the motherboard know whether parity or non-parity RAM is
> installed.
>
> This is really an issue about where hardware initialization should occur. The
> real-mode setup.S seems to be the intended place to do this sort of thing, but
> very few people like writing assembler code so it tends to clutter up the kernel
> proper. I have a few ideas about this. Maybe something will happen in a few
> weeks.
Hmmm I don't think so. Hardware initialization should occour at BIOS
stage. The kernel should rely only on the fact that an NMI has occurred.
If so, there are some facts we can consider:
1) NMIs are supported by the MB
2) NMI interrupt is enabled
3) (If bit 3 is clear, bit 6 should be set) OR (if bit 4 is clear, bit 7
should be set).
4) If 3) fails, this MB don't support this mechanism.
I know this is not very strong, we should find a way to know for sure if
the MB is supporting this mechanism.
Ciao,
Riccardo.