I belive that since the MMX registers are overlayed over the
FPUs floating point registers, any OS which properly performs context
switching for the FPU will support MMX by default. This was probably a
neccesary design aspect for Intel, since it seems to have made a definate
commitment towards backward compatability. (If they were gonna add more
registers, they might as well add more general purpose ones to.)
Jeremy
> Hi,
>
> I have spent much time reading the Intel web pages. But still have
> questions.
>
> I have a video processing task that can be performed in real time using
> the mmx instruction set (verified on windoz). Are the mmx extensions
> supported by the kernel (during context switches etc.)? I could not
> find any of the mmx instruction opcodes in the gas sources. Is it
> supported in some hidden way, to be supported, or is there another
> assembler?
>
> I need speed, smp and mmx (acronym city:-( Bad as the govt;-). Does a
> pair of 266 mHz Pentium IIs on an ASUS P/I-P65UP5 / c-PKND represent a
> viable smp configuration? Any ideas on performance relative to the lack
> of SDRAM, fp errors etc. would be appreciated.
>
> thanks
> don
> --
> *******************************************************************
> * Don Fisher dfisher@as.arizona.edu *
> * MMT Observatory VOICE: (520)621-7647 *
> * University of Arizona FAX: (520)670-5740 *
> * Tucson, AZ 85721 *
> *******************************************************************
>
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