I am getting full flip buffers with only an ISDN PPP connection
and a single login on a VT. Don't know how many pty's are in
use, but the system can be fairly idle except for a large FTP
in progress when the flip buffer overflows occur. I am rarely
paging on this system.
There was a false assumption made in the serial code. It assumed
that an entire run through the timer task queue was made every
clock tick. That may or may not happen, depending on how many
other tasks need to be run, whether we have to sleep, and the
number of interrupts occuring.
I can increase the rate the the flip buffer overflows a number
of ways. Enabling 'kdebug 1' in pppd and decreasing the receive
FIFO trigger level both do this. Though decreasing the FIFO
trigger level decreases the number of FIFO overflows. This
shows that increasing the rate of interrupts or increasing
the amount of bottom half processing will reduce the rate
at which the buffers are flipped.
Your theory may have a larger impact than I believe it does, but
I would need to see some profiling data to prove it.
-Rob